Renesas RX100 Series User Manual page 388

RX13T Group
(b) Free-Running Count Operation and Periodic Count Operation
Immediately after a reset, the TCNT counters are all designated as free-running counters. When the CSTn bit in TSTRA
or MTU5.TSTR is set to 1, the corresponding TCNT counter starts up-count operation as a free-running counter. When
TCNT overflows (from FFFFh to 0000h), an interrupt request is issued to the CPU if the corresponding TIER.TCIEV bit
is 1. After an overflow, TCNT starts counting up again from 0000h.
Figure 19.5 illustrates free-running counter operation.
CSTn bit
TCIV interrupt signal
Figure 19.5 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, TCNT for the relevant channel performs periodic count
operation. TGR for setting the period is designated as an output compare register, and counter clearing by compare match
is selected by means of bits CCLR[2:0] in TCR. After the settings have been made, TCNT starts up-count operation as a
periodic counter when the CSTn bit in TSTRA or MTU5.TSTR is set to 1. When the count matches the value in TGR,
TCNT becomes 0000h.
If the value of the corresponding TIER.TGIE bit is 1 at this point, an interrupt request is issued to the CPU. After a
compare match, TCNT starts counting up again from 0000h.
Figure 19.6 illustrates periodic counter operation.
CSTn bit
TGI interrupt signal
Figure 19.6 Periodic Counter Operation
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
TCNT value
FFFFh
0000h
TCNT value
TGR
0000h
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Counter cleared by TGR compare match
Time
Time
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