Operation In Simple Spi Mode - Renesas RX100 Series User Manual

RX13T Group
23.8

Operation in Simple SPI Mode

As an extended function, the SCI supports a simple SPI mode that handles transfer among one or multiple master devices
and multiple slave devices.
Making the settings for clock synchronous mode (SCMR.SMIF = 0, SIMR1.IICM = 0, SMR.CM = 1) plus setting the
SSE bit in the SPMR to 1 places the SCI in simple SPI mode. However, the SS pin function on the master side is
unnecessary for connection of the device used as the master in simple SPI mode when the configuration only has a single
master, so set the SSE bit in the SPMR to 0 in such cases.
Figure 23.56 shows an example of connections for simple SPI mode. Control a general port pin to produce the SS
output signal from the master.
In simple SPI mode, data are transferred in synchronization with clock pulses in the same way as in clock synchronous
mode. One character of data for transfer consists of 8 bits of data, and parity bits cannot be appended to this. The data can
be inverted by setting the SCMR.SINV bit to 1.
Since the receiver and transmitter are independent of each other within the SCI module, full-duplex communications are
possible, with a common clock signal. Furthermore, since both the transmitter and receiver have a double-buffered
structure, writing of further transmit data while transmission is in progress and reading of previously received data while
reception is in progress are both possible. Continuous transfer is thus possible.
Device 1 (master)
SMOSIn (output)
Note 1. The SSn# input is not required in a single-master system
Figure 23.56 Example of Connections via a Simple SPI Mode (In Single Master Mode, SPMR.SSE Bit = 0)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Port pin (output)
Port pin (output)
SSn# (input)
1
*
SCKn (output)
SMISOn (input)
(the interface is used with the setting SPMR.SSE = 0).
23. Serial Communications Interface (SCIg, SCIh)
Device 2 (slave)
SSn# (input)
SCKn (input)
SMISOn (output)
SMOSIn (input)
Device 3 (slave)
SSn# (input)
SCKn (input)
SMISOn (output)
SMOSIn (input)
Page 690 of 1041