Renesas RX100 Series User Manual page 607

RX13T Group
Table 23.12 Clock Source Settings
SMR.CKS[1:0] Bit Setting
0 0
0 1
1 0
1 1
Table 23.13 Base Clock Settings in Smart Card Interface Mode
SCMR.BCP2 Bit Setting
0
0
0
0
1
1
1
1
Table 23.14 lists examples of N settings in BRR in normal asynchronous mode. Table 23.15 lists the maximum bit rate
settable for each operating frequency. Examples of BRR (N) settings in clock synchronous mode and simple SPI mode
are listed in Table 23.18 . Examples of BRR (N) settings in smart card interface mode are listed in Table 23.20 .
Examples of BRR (N) settings in simple I
base clock cycles S in a 1-bit data transfer time can be selected. For details, refer to section 23.6.4, Receive Data
Sampling Timing and Reception Margin . Table 23.16 and Table 23.19 list the maximum bit rates with external
clock input.
When either the SEMR.ABCS or BGDM bit is set to 1 in asynchronous mode, the bit rate becomes twice that listed in
Table 23.14 . When both of those bits are set to 1, the bit rate becomes four times the listed value.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Clock Source n
PCLK 0
PCLK/4 1
PCLK/16 2
PCLK/64 3
SMR.BCP[1:0] Bit Setting
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
2
C mode are listed in Table 23.22 . In smart card interface mode, the number of
23. Serial Communications Interface (SCIg, SCIh)
Base Clock Cycles for 1-bit Period
93 clock cycles
128 clock cycles
186 clock cycles
512 clock cycles
32 clock cycles
64 clock cycles
372 clock cycles
256 clock cycles
S
93
128
186
512
32
64
372
256
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