Operation In Clock Synchronous Mode; Clock - Renesas RX100 Series User Manual

RX13T Group
23.5

Operation in Clock Synchronous Mode

Figure 23.22 shows the data format for clock synchronous serial data communications.
In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in
transfer data consists of 8-bit data. In clock synchronous mode, no parity bit can be added.
In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data
reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is
output, the communication line holds the last bit output state.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communications by use of a
common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data
can be written during transmission or the previous receive data can be read during reception, enabling continuous data
transfer.
Synchronization

clock

Serial data
Don't care
Note 1. Holds a high level except during continuous transfer.
Figure 23.22 Data Format in Clock Synchronous Serial Communications (LSB First)
23.5.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the
SCKn pin can be selected, according to the setting of the SCR.CKE[1:0] bits.
When the SCI is operated on an internal clock, the synchronization clock is output from the SCKn pin. Eight
synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is
held high. However, when only data reception is performed while the CTS function is disabled, the synchronization
clock output is started at the same time when the SCR.RE bit set to 1. The synchronization clock is stopped at the high
level when an overrun error occurs or the SCR.RE bit is set to 0.
When only data reception is performed and the CTS function is enabled, the clock output is not started even when the
SCR.RE bit set to 1 if the CTSn# pin input is high when the SCR.RE bit is 0. The synchronization clock output is started
when the SCR.RE bit is set to 1 and the CTSn# pin input is low. After that, if the CTSn# pin input is high on completion
of the frame reception, the synchronization clock output is stopped at the high level. If the CTSn# pin input continues to
be low, the synchronization clock is stopped at the high level when an overrun error occurs or the SCR.RE bit is set to 0.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
One unit of transfer data (character or frame)
1
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LSB
Bit 0 Bit 1
23. Serial Communications Interface (SCIg, SCIh)
Bit 2 Bit 3 Bit 4
MSB
Bit 5 Bit 6 Bit 7
Don't care
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