A/D Control Register (Adcsr) - Renesas RX100 Series User Manual

RX13T Group
26.2.3

A/D Control Register (ADCSR)

Address(es): S12AD.ADCSR 0008 9000h
b15 b14
ADST ADCS[1:0]
Value after reset: 0 0
Bit Symbol
b4 to b0 DBLANS[4:0]
b5 —
b6 GBADIE
b7 DBLE
b8 EXTRG
b9 TRGE
b11, b10 —
b12 ADIE
b14, b13 ADCS[1:0]
b15 ADST
Note 1. Starting A/D conversion using an external pin (asynchronous trigger)
Set the ADCSR.TRGE and EXTRG bits to 1 while a high-level signal is input to the external pin (ADTRG0#). Then, if the
ADTRG0# signal is changed to low, the falling edge is detected and the scan process is started. In this case, the pulse width of
the low-level input must be at least 1.5 clock cycles of PCLK.
ADCSR sets double trigger mode, A/D conversion start trigger; enables/disables scan end interrupt; selects the scan
mode; and starts or stops A/D conversion.
DBLANS[4:0] Bits (Double Trigger Channel Select)
The DBLANS[4:0] bits select one of the channels for A/D conversion data duplication in double trigger mode. The A/D
conversion results of the analog input of the channel selected by the DBLANS[4:0] bits are stored into the A/D data
register y when conversion is started by the first trigger, and into the A/D data duplication register when started by the
second trigger. Table 26.5 shows selection of the channel for double triggered operation.
When double trigger mode is selected, the channels selected by the ADANSA0 register are invalid, and the channel
selected by the DBLANS[4:0] bits is subjected to A/D conversion instead.
When double trigger mode is selected in group scan mode, double trigger mode operation is performed for group A only
and not performed for group B or C. Also, in double trigger mode, the analog inputs of multiple internal reference
voltage cannot be selected for group A, but can be selected for groups B and C.
The DBLANS[4:0] bits should be set while the ADST bit is 0. They should not be set simultaneously when 1 is written
to the ADST bit.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
ADIE — —
0 0 0 0
Bit Name Description
Double Trigger These bits select one analog input channel for double triggered
Channel Select operation. The setting is only effective while double trigger mode is
selected.
Reserved This bit is read as 0. The write value should be 0.
Group B Scan End 0: Disables interrupt generation upon group B scan completion.
Interrupt Enable 1: Enables interrupt generation upon group B scan completion.
Double Trigger Mode 0: Deselects double trigger mode.
Select 1: Selects double trigger mode.
1
Trigger Select* 0: A/D conversion is started by synchronous trigger.
1: A/D conversion is started by asynchronous trigger.
Trigger Start Enable 0: Disables A/D conversion to be started by synchronous or
asynchronous trigger.
1: Enables A/D conversion to be started by synchronous or
asynchronous trigger.
Reserved These bits are read as 0. The write value should be 0.
Scan End Interrupt 0: Disables interrupt generation upon scan completion.
Enable 1: Enables interrupt generation upon scan completion.
Scan Mode Select
b14 b13
0 0: Single scan mode
0 1: Group scan mode
1 0: Continuous scan mode
1 1: Setting prohibited
A/D Conversion Start 0: Stops A/D conversion process.
1: Starts A/D conversion process.
b9 b8 b7 b6
TRGE EXTRG DBLE GBADI
E
0 0 0 0
26. 12-Bit A/D Converter (S12ADF)
b5 b4 b3 b2
— DBLANS[4:0]
0 0 0 0
Page 815 of 1041
b1 b0
0 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W