Dtc Sequence Transfer Enable Register (Dtcsqe); Dtc Address Displacement Register (Dtcdisp) - Renesas RX100 Series User Manual

RX13T Group
16.2.15

DTC Sequence Transfer Enable Register (DTCSQE)

Address(es): DTC.DTCSQE 0008 2416h
b15 b14
ESPSE
—
L
Value after reset: 0 0
Bit Symbol
b7 to b0 VECN[7:0]
b14 to b8 —
b15 ESPSEL
The DTCSQE register is used to specify sequence transfer. Follow Figure 16.24 for details on the setting procedure.
VECN[7:0] Bit (Sequence Transfer Vector Number Setting)
This bit is used to specify for which vector number to perform sequence transfer. Sequence transfer can occur only for
this trigger source.
section 14.3.1, Interrupt Vector Table in section 14, Interrupt Controller (ICUb) shows the relationship between the
trigger source and the vector number.
ESPSEL Bit (Sequence Transfer Enable)
The ESPSEL bit specifies whether sequence transfer is used.
Set the DTCADMOD.SHORT bit to 0 (full address mode), when setting the ESPSEL bit to 1.
16.2.16

DTC Address Displacement Register (DTCDISP)

Address(es): DTC.DTCDISP 0008 2418h
b31 b30
0 0
Value after reset:
b15 b14
0 0
Value after reset:
The DTCDISP register is used to specify the displacement value to add to the DTC transfer source address.
If MRC.DISPE bit is 1, the value SAR + DTCDISP is used as the transfer source address.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
— — — —
0 0 0 0
Bit Name
Sequence Transfer Vector
Number Setting
Reserved
Sequence Transfer Enable
b29 b28 b27 b26
0 0 0 0
b13 b12 b11 b10
0 0 0 0
b9 b8 b7 b6
— —
0 0 0 0
Description
Specify the vector number by which a sequence transfer is
enabled.
The value is only valid when the ESPSEL bit is 1.
These bits are read as 0. The write value should be 0.
0: Sequence transfer is disabled.
1: Sequence transfer is enabled.
b25 b24 b23 b22
0 0 0 0
b9 b8 b7 b6
0 0 0 0
16. Data Transfer Controller (DTCb)
b5 b4 b3 b2
VECN[7:0]
0 0 0 0
b21 b20 b19 b18
0 0 0 0
b5 b4 b3 b2
0 0 0 0
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b1 b0
0 0
R/W
R/W
R
R/W
b17 b16
0 0
b1 b0
0 0