Register Descriptions; E2 Dataflash Control Register (Dflctl) - Renesas RX100 Series User Manual

RX13T Group
31.4

Register Descriptions

31.4.1

E2 DataFlash Control Register (DFLCTL)

Address(es): FLASH.DFLCTL 007F C090h
b7 b6
— —
0 0
Value after reset:
Bit Symbol Bit Name
b0 DFLEN E2 DataFlash Access
Enable
b7 to b1 — Reserved
Note 1. Unique ID read, start-up area information program, and access window information program
The DFLCTL register is used to enable or disable access (read, program, and erase) to the E2 DataFlash and access
(unique ID read, start-up area information program, and access window information program) to the extra area in P/E
mode.
When reading, programming, and erasing the E2 DataFlash, set the DFLCTL.DFLEN bit to 1 and wait for the E2
DataFlash STOP recovery time (tDSTOP) to elapse before reading the E2 DataFlash and entering E2 DataFlash P/E
mode. Do not read the E2 DataFlash or enter E2 DataFlash P/E mode until tDSTOP has elapsed.
Refer to section 31.7.1, Sequencer Modes for details on E2 DataFlash P/E mode. Refer to section 32, Electrical
Characteristics for E2 DataFlash STOP recovery time (tDSTOP).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
0 0 0 0
Description
0: Access to E2 DataFlash and access to the extra area in P/E mode*
disabled
1: Access to E2 DataFlash and access to the extra area in P/E mode*
enabled
These bits are read as 0. The write value should be 0.
b1 b0
— DFLEN
0 0
31. Flash Memory (FLASH)
R/W
1
R/W
1
R/W
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