Dtc Mode Register B (Mrb) - Renesas RX100 Series User Manual

RX13T Group
16.2.2

DTC Mode Register B (MRB)

Address(es): (inaccessible directly from the CPU)
b7 b6
CHNE CHNS DISEL
Value after reset: x x
x: Undefined
Bit Symbol Bit Name
b0 SQEND Sequence Transfer End
b1 INDX Index Table Reference
b3, b2 DM[1:0] Transfer Destination Address
Addressing Mode
b4 DTS DTC Transfer Mode Select
b5 DISEL DTC Interrupt Select
b6 CHNS DTC Chain Transfer Select
b7 CHNE DTC Chain Transfer Enable
Note 1. Set the MRA.MD[1:0] bits to 00b (normal transfer mode) when setting the INDX bit to 1.
MRB register is used to select the DTC operating mode and cannot be accessed directly from the CPU.
SQEND Bit (Sequence Transfer End)
The SQEND bit selects whether to continue or end sequence transfer. Refer to Table 16.2 for details.
This bit can only be set to 1 for transfer information referred to by the DTC index table. Set this bit to 0 for transfer
information referred to by the DTC vector table.
INDX Bit (Index Table Reference)
When the value of the INDX bit in transfer information that is read is 1, a sequence transfer proceeds. Refer to Table
16.2 for details.
Set this bit to 0 for transfer information which is not associated with sequence transfer or is not intended to start sequence
transfer. Do not allow transfer requests to be generated by the sources different from that specified in the DTCSQE
register but having the INDX bit set to 1.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
DTS DM[1:0] INDX SQEND
x x x x
Description
0: Continue the sequence transfer
1: End the sequence transfer
0: Does not refer to the index table
1: Refers the index table based on the transferred data*
b3 b2
0 0: The address in the DAR register is fixed.
0 1: The address in the DAR register is fixed.
1 0: The DAR value is incremented after data transfer.
1 1: The DAR value is decremented after data transfer.
0: Transfer destination side is repeat area or block area.
1: Transfer source side is repeat area or block area.
0: An interrupt request to the CPU is generated on completion of the
specified number of data transfers.
1: An interrupt request to the CPU is generated for each data transfer.
0: Chain transfer is performed on completion of each transfer.
1: Chain transfer is performed only when the transfer counter is
changed from 1 to 0 or 1 to CRAH.
0: Chain transfer is disabled.
1: Chain transfer is enabled.
b1 b0
x x
(Write-back to DAR is skipped.)
(Write-back to DAR is skipped.)
(+1 when the MRA.SZ[1:0] bits are 00b, +2 when 01b, +4 when
10b)
(–1 when the MRA.SZ[1:0] bits are 00b, –2 when 01b, –4 when
10b)
16. Data Transfer Controller (DTCb)
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