Timer Gate Control Register A (Tgcra) - Renesas RX100 Series User Manual

RX13T Group
19.2.24

Timer Gate Control Register A (TGCRA)

Address(es): MTU.TGCRA 0009 520Dh
b7 b6
— BDC
Value after reset: 1 0
Bit Symbol Bit Name
b0 UF Output Phase Switch
b1 VF
b2 WF
b3 FB External Feedback Signal Enable
b4 P Positive-Phase Output (P) Control
b5 N Negative-Phase Output (N) Control
b6 BDC Brushless DC Motor
b7 — Reserved
TGCRA controls the output waveform necessary for brushless DC motor control in reset-synchronized PWM mode and
complementary PWM mode. TGCRA register settings are ineffective for anything other than complementary PWM
mode and reset-synchronized PWM mode.
UF, VF, and WF Bits (Output Phase Switch)
The setting of these bits is valid only when the FB bit is set to 1. In this case, the setting of b0 to b2 is used instead of the
external input. Refer to Table 19.39 for details.
FB Bit (External Feedback Signal Enable)
This bit selects whether the positive-/negative-phase output is switched automatically with the TGRA, TGRB, and
TGRC input capture signals in MTU0 or by writing 0 or 1 to bits 2 to 0 in TGCRA.
When the TGCRA.FB bit is 0, output of MTU3 and MTU4 can be switched with the TGRA, TGRB, and TGRC input
capture signals in MTU0.
P Bit (Positive-Phase Output (P) Control)
This bit selects the level output or the reset-synchronized PWM/complementary PWM output for the positive-phase
output pins (MTIOC3B, MTIOC4A, and MTIOC4B pins).
N Bit (Negative-Phase Output (N) Control)
This bit selects the level output or the reset-synchronized PWM/complementary PWM output for the negative-phase
output pins (MTIOC3D, MTIOC4C, and MTIOC4D pins).
BDC Bit (Brushless DC Motor)
This bit selects whether to make the functions of TGCRA effective or ineffective.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
N P FB WF
0 0 0 0
Description
These bits turn on or off the positive-phase/negative-phase
output. The setting of these bits is valid only when the FB bit is
set to 1. In this case, the setting of b0 to b2 is used instead of
the external input. Refer to Table 19.39.
0: Output is switched by external input (input sources are
1: Output is switched by software (TGCRA's UF, VF, and WF
0: Level output
1: Reset-synchronized PWM or complementary PWM output
0: Level output
1: Reset-synchronized PWM or complementary PWM output
0: Ordinary output
1: Functions of this register are made effective
This bit is read as 1. The write value should be 1.
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
VF UF
0 0
TGRA, TGRB, and TGRC input capture signals in MTU0)
settings)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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