Register Descriptions; I 2 C-Bus Control Register 1 (Iccr1) - Renesas RX100 Series User Manual

RX13T Group
24.2

Register Descriptions

2
24.2.1 I C-bus Control Register 1 (ICCR1)
Address(es): RIIC0.ICCR1 0008 8300h
b7 b6
ICE IICRST
Value after reset: 0 0
Bit Symbol Bit Name
b0 SDAI SDA Line Monitor
b1 SCLI SCL Line Monitor
b2 SDAO SDA Output Control/Monitor
b3 SCLO SCL Output Control/Monitor
b4 SOWP SCLO/SDAO Write Protect
b5 CLO Extra SCL Clock Cycle Output
2
b6 IICRST I C-bus Interface Internal
Reset
2
b7 ICE I C-bus Interface Enable
SDAO Bit (SDA Output Control/Monitor) and SCLO Bit (SCL Output Control/Monitor)
These bits are used to directly control the SDA0 and SCL0 signals output from the RIIC.
When writing to these bits, also write 0 to the SOWP bit.
The result of setting these bits is input to the RIIC via the input buffer. When slave mode is selected, a start condition
may be detected and the bus may be released depending on the bit settings.
Do not rewrite these bits during a start condition, stop condition, restart condition, or during transmission or reception.
Operation after rewriting under the above conditions is not guaranteed.
When reading these bits, the state of signals output from the RIIC can be read.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
CLO SOWP SCLO SDAO
0 1 1 1
Description
0: SDA0 line is low.
1: SDA0 line is high.
0: SCL0 line is low.
1: SCL0 line is high.
 Read:
0: The RIIC has driven the SDA0 pin low.
1: The RIIC has released the SDA0 pin.
 Write:
0: The RIIC drives the SDA0 pin low.
1: The RIIC releases the SDA0 pin.
 Read:
0: The RIIC has driven the SCL0 pin low.
1: The RIIC has released the SCL0 pin.
 Write:
0: The RIIC drives the SCL0 pin low.
1: The RIIC releases the SCL0 pin.
0: SCLO and SDAO bits can be written.
1: SCLO and SDAO bits are protected.
0: Does not output an extra SCL clock cycle (default).
1: Outputs an extra SCL clock cycle.
0: Releases the RIIC reset or internal reset.
1: Initiates the RIIC reset or internal reset.
0: Disable (SCL0 and SDA0 pins in inactive state)
1: Enable (SCL0 and SDA0 pins in active state)
b1 b0
SCLI SDAI
1 1
(High level output is achieved through an external pull-up
resistor.)
(This bit is read as 1.)
(The CLO bit is cleared automatically after one clock cycle is
output.)
(Clears the bit counter and the SCL0/SDA0 output latch)
(Combined with the IICRST bit to select either RIIC or internal
reset.)
2
24. I C-bus Interface (RIICa)
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
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