Renesas RX100 Series User Manual page 157

RX13T Group
CACREF
Main clock
HOCO clock
LOCO clock
IWDTCLK
PCLKB
CFME: Bit in CACR0
CACREFE, FMCS[2:0], TCSS[1:0], EDGES[1:0]: Bits in CACR1
RPS, RSCS[2:0], RCDS[1:0], DFS[1:0]: Bits in CACR2
CAICR: CAC interrupt control register
CASTR: CAC status register
CAULVR: CAC upper-limit value setting register
CALLVR: CAC lower-limit value setting register
CACNTBR: CAC counter buffer register
Figure 10.1 CAC Block Diagram
Table 10.2 shows the pin configuration of the CAC.
Table 10.2 Pin Configuration of CAC
Pin Name I/O
CACREF Input
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
DFS[1:0]
CACREFE
Digital filter
RSCS[2:0] RCDS[1:0]
1/32
Measurement 1/128
reference
1/1024
clock select
circuit
1/8192
FMCS[2:0] TCSS[1:0]
Measurement
target clock
1/4
Measurement
target clock
1/8
select circuit
1/32
Function
Measurement reference clock input pin
10. Clock Frequency Accuracy Measurement Circuit (CAC)
DFS[1:0]
EDGES[1:0]
Edge detection
circuit
RPS
Valid edge signal
CFME
Count source
clock
16-bit counter
CACNTBR
Comparator
CAULVR CALLVR
Internal peripheral bus
Overflow interrupt request
Interrupt control
Measurement end interrupt
circuit
request
Frequency error interrupt
request
CAICR CASTR
Page 157 of 1041