Noise Filter Control Register N (Nfcrn) (N = 0 To 4, C) - Renesas RX100 Series User Manual

RX13T Group
19.2.32

Noise Filter Control Register n (NFCRn) (n = 0 to 4, C)

 MTU0.NFCR0, MTU1.NFCR1, MTU2.NFCR2, MTU3.NFCR3, MTU4.NFCR4
Address(es): MTU0.NFCR0 0009 5290h, MTU1.NFCR1 0009 5291h, MTU2.NFCR2 0009 5292h, MTU3.NFCR3 0009 5293h,
MTU4.NFCR4 0009 5294h
b7 b6
— —
0 0
Value after reset:
Bit Symbol Bit Name
b0 NFAEN Noise Filter A Enable
b1 NFBEN Noise Filter B Enable
b2 NFCEN Noise Filter C Enable*
b3 NFDEN Noise Filter D Enable*
b5, b4 NFCS[1:0] Noise Filter Clock Select
b7, b6 — Reserved
Note 1. These bits are reserved in MTU1 and MTU2. These bits are read as 0 and writing to them has no effect.
The NFCRn register (n = 0 to 4) sets the noise filter function of input capture pins for the corresponding channel.
NFAEN Bit (Noise Filter A Enable)
This bit disables or enables the noise filter for input from the MTIOCnA pin. Since changing the value of the bit may
lead to the internal generation of an unexpected edge, select the output compare function for the relevant pin in the timer
I/O control register or set the TMDR.MD[3:0] bits to a value other than that for normal mode (0000b) before doing so.
NFBEN Bit (Noise Filter B Enable)
This bit disables or enables the noise filter for input from the MTIOCnB pin. Since changing the value of the bit may lead
to the internal generation of an unexpected edge, select the output compare function for the relevant pin in the timer I/O
control register or set the TMDR.MD[3:0] bits to a value other than that for normal mode (0000b) before doing so.
NFCEN Bit (Noise Filter C Enable)
This bit disables or enables the noise filter for input from the MTIOCnC pin. Since changing the value of the bit may lead
to the internal generation of an unexpected edge, select the output compare function for the relevant pin in the timer I/O
control register or set the TMDR.MD[3:0] bits to a value other than that for normal mode (0000b) before doing so.
NFDEN Bit (Noise Filter D Enable)
This bit disables or enables the noise filter for input from the MTIOCnD pin. Since changing the value of the bit may
lead to the internal generation of an unexpected edge, select the output compare function for the relevant pin in the timer
I/O control register or set the TMDR.MD[3:0] bits to a value other than that for normal mode (0000b) before doing so.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
NFCS[1:0] NFDEN NFCEN NFBEN NFAEN
0 0 0 0
Description
0: The noise filter for the MTIOCnA pin is disabled.
1: The noise filter for the MTIOCnA pin is enabled.
0: The noise filter for the MTIOCnB pin is disabled.
1: The noise filter for the MTIOCnB pin is enabled.
1 0: The noise filter for the MTIOCnC pin is disabled.
1: The noise filter for the MTIOCnC pin is enabled.
1
0: The noise filter for the MTIOCnD pin is disabled.
1: The noise filter for the MTIOCnD pin is enabled.
These bits are read as 0. The write value should be 0.
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
0 0
b5 b4
0 0: PCLKB/1
0 1: PCLKB/8
1 0: PCLKB/32
1 1: Clock source for counting
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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