Renesas RX100 Series User Manual page 584

RX13T Group
Table 23.2 SCIh Specifications (2/2)
Item
Asynchronous Data length
mode
Transmission stop bit
Parity
Receive error detection
Hardware flow control
Start-bit detection
Break detection
Clock source
Double-speed mode
Multi-processor
communications function
Noise cancellation
Clock Data length
synchronous
Receive error detection
mode
Hardware flow control
Smart card Error processing
interface mode
Data type
2
Simple I C Transfer format
mode
Operating mode
Transfer rate
Noise cancellation
Simple SPI Data length
bus
Detection of errors
SS input pin function
Clock settings
Start Frame transmission  Output of a low level as the Break Field over a specified width and generation of
Extended
serial mode
Start Frame reception
I/O control function
Timer function
Bit rate modulation function
2
Note 1. In simple I C mode, only MSB first is available.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Description
7, 8, or 9 bits
1 or 2 bits
Even parity, odd parity, or no parity
Parity, overrun, and framing errors
CTSn# and RTSn# pins can be used in controlling transmission/reception.
Low level or falling edge is selectable.
When a framing error occurs, a break can be detected by reading the RXDn pin level
directly.
An internal or external clock can be selected.
Transfer rate clock input from the MTU can be used.
Baud rate generator double-speed mode is selectable.
Serial communication among multiple processors
The signal paths from input on the RXDn pins incorporate digital noise filters.
8 bits
Overrun error
CTSn# and RTSn# pins can be used in controlling transmission/reception.
An error signal can be automatically transmitted when detecting a parity error during
reception
Data can be automatically retransmitted when receiving an error signal during transmission
Both direct convention and inverse convention are supported.
2
I C-bus format
Master (single-master operation only)
Fast mode is supported (refer to section 23.2.11, Bit Rate Register (BRR) to set the
transfer rate).
The signal paths from input on the SSCLn and SSDAn pins incorporate digital noise filters,
and the interval for noise cancellation is adjustable.
8 bits
Overrun error
Applying the high level to the SSn# pin can cause the output pins to enter the
high-impedance state.
Four kinds of settings for clock phase and clock polarity are selectable.
interrupts on completion
 Detection of bus collisions and the generation of interrupts on detection
 Detection of the Break Field low width and generation of an interrupt on detection
 Comparison of Control Fields 0 and 1 and generation of an interrupt when the two match
 Two kinds of data for comparison (primary and secondary) can be set in Control Field 1.
 A priority interrupt bit can be set in Control Field 1.
 Handling of Start Frames that do not include a Break Field
 Handling of Start Frames that do not include a Control Field 0
 Function for measuring bit rates
 Selectable polarity for TXDX12 and RXDX12 signals
 Selection of a digital filter for the RXDX12 signal
 Half-duplex operation employing RXDX12 and TXDX12 signals multiplexed on the same
pin
 Selectable timing for the sampling of data received through RXDX12
 Usable as a reloading timer
Correction of outputs from the on-chip baud rate generator can reduce errors.
23. Serial Communications Interface (SCIg, SCIh)
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