Register Descriptions; Compare Match Timer Start Register 0 (Cmstr0); Compare Match Timer Control Register (Cmcr) - Renesas RX100 Series User Manual

RX13T Group
21.2

Register Descriptions

21.2.1

Compare Match Timer Start Register 0 (CMSTR0)

Address(es): 0008 8000h
b15 b14
— —
0 0
Value after reset:
Bit Symbol Bit Name
b0 STR0 Count Start 0
b1 STR1 Count Start 1
b15 to b2 — Reserved
21.2.2

Compare Match Timer Control Register (CMCR)

Address(es): CMT0.CMCR 0008 8002h, CMT1.CMCR 0008 8008h
b15 b14
— —
0 0
Value after reset:
x: Undefined
Bit Symbol Bit Name
b1, b0 CKS[1:0] Clock Select
b5 to b2 — Reserved
b6 CMIE Compare Match Interrupt
Enable
b7 — Reserved
b15 to b8 — Reserved
CKS[1:0] Bits (Clock Select)
These bits select the count source from four frequency dividing clocks obtained by dividing the peripheral module clock
(PCLK).
When the CMSTR0.STRn (n = 0, 1) bit is set to 1, the CMCNT counter starts counting up on the clock selected with the
CKS[1:0] bits.
CMIE Bit (Compare Match Interrupt Enable)
The CMIE bit enables or disables compare match interrupt (CMIn) (n = 0, 1) generation when the CMCNT counter and
the CMCOR register values match.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
— — — —
0 0 0 0
Description
0: CMT0.CMCNT count is stopped.
1: CMT0.CMCNT count is started.
0: CMT1.CMCNT count is stopped.
1: CMT1.CMCNT count is started.
These bits are read as 0. The write value should be 0.
b13 b12 b11 b10
— — — —
0 0 0 0
Description
b1 b0
0 0: PCLK/8
0 1: PCLK/32
1 0: PCLK/128
1 1: PCLK/512
These bits are read as 0. The write value should be 0.
0: Compare match interrupt (CMIn) disabled
1: Compare match interrupt (CMIn) enabled
This bit is read as undefined. The write value should be 1.
These bits are read as 0. The write value should be 0.
b9 b8 b7 b6
— — — —
0 0 0 0
b9 b8 b7 b6
— — — CMIE
0 0 x 0
21. Compare Match Timer (CMT)
b5 b4 b3 b2
— — — — STR1
0 0 0 0
b5 b4 b3 b2
— — — —
0 0 0 0
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b1 b0
STR0
0 0
R/W
R/W
R/W
R/W
b1 b0
CKS[1:0]
0 0
R/W
R/W
R/W
R/W
R/W
R/W