Transmit Data Register H, L, Hl (Tdrh, Tdrl, Tdrhl); Transmit Shift Register (Tsr) - Renesas RX100 Series User Manual

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Transmit Data Register H, L, HL (TDRH, TDRL, TDRHL)

 Transmit Data Register H (TDRH)

Address(es): SCI1.TDRH 0008 A02Eh, SCI5.TDRH 0008 A0AEh, SCI12.TDRH 0008 B30Eh

 Transmit Data Register L (TDRL)

Address(es): SCI1.TDRL 0008 A02Fh, SCI5.TDRL 0008 A0AFh, SCI12.TDRL 0008 B30Fh

 Transmit Data Register HL (TDRHL)

Address(es): SCI1.TDRHL 0008 A02Eh, SCI5.TDRHL 0008 A0AEh, SCI12.TDRHL 0008 B30Eh

Value after reset:

TDRH and TDRL are 8-bit registers that store transmit data. Use these registers when asynchronous mode and 9-bit data

length are selected.

TDRL is the shadow register of TDR; i.e. access to TDRL is equivalent to access to TDR.

When empty space is detected in the TSR register, the transmit data stored in the TDRH and TDRL registers is

transferred to TSR; i.e., transmitting is started.

The TSR, TDRH and TDRL registers have a double-buffered construction to realize continuous reception. When the

next data to be transmitted is stored in the TDRL register after one frame of data has been transmitted, the transmitting

operation is continued by transfer to the TSR register.

The CPU can read and write to the TDRH and TDRL registers. Bits 0 to 7 in RDRH are fixed to 1. These bits are read as

1. The write value should be 1.

Writing transmit data to the TDRH and TDRL registers should be performed only once in the order from TDRH to

TDRL when a transmit data empty interrupt (TXI) request is issued.

The TDRHL register can be accessed in 16-bit units.

TSR is a shift register that transmits serial data.

To perform serial data transmission, the SCI first automatically transfers transmit data from TDR to TSR, and then sends

the data to the TXDn pin.

TSR cannot be directly accessed by the CPU.

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

23. Serial Communications Interface (SCIg, SCIh)

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