Renesas RX100 Series User Manual page 431

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Dead Time Suppressing

Dead time generation is suppressed by setting the TDER bit in the timer dead time enable register (TDERA) to 0.

TDERA can be set to 0 only when 0 is written to it after reading TDER = 1.

MTU3.TGRA and MTU3.TGRC should be set to 1/2 PWM period + 1 and the timer dead time data register (TDDRA)

should be set to 1.

By the above settings, PWM waveforms without dead time can be obtained. Figure 19.48 shows an example of

operation without dead time (MTU3 and MTU4).

Buffer register

Temporary register

Compare register

Positive-phase

Negative-phase

Figure 19.48

Example of Operation without Dead Time (MTU3 and MTU4)

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

Transfer from temporary

to compare register

Initial output

Initial output

19. Multi-Function Timer Pulse Unit 3 (MTU3c)

(Output waveform is active-low)

Transfer from temporary

to compare register

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