Register Descriptions; Comparator Control Register (Cmpctl) - Renesas RX100 Series User Manual

RX13T Group
28.2

Register Descriptions

28.2.1

Comparator Control Register (CMPCTL)

Address(es): CMPC0.CMPCTL 000A 0C80h, CMPC1.CMPCTL 000A 0CA0h, CMPC2.CMPCTL 000A 0CC0h
b7 b6
HCMP
CDFS[1:0]
ON
0 0
Value after reset:
Bit Symbol Bit Name
b0 CINV Comparator Output Polarity Select
1,
*
b1 COE Comparator Output Enable
b2 — Reserved
b4, b3 CEG[1:0] Comparator Edge Interrupt Detection
Select
b6, b5 CDFS[1:0] Noise Filter Sampling Select*
b7 HCMPON Comparator Operation Enable*
Note 1. Rewrite the CDFS[1:0] and CINV bits only after disabling the comparator output (COE bit = 0).
Note 2. If the CDFS[1:0] bits are changed from 00b (noise filter not used) to a value other than 00b (noise filter used), allow four
sampling times to elapse until the filter output is updated, and then use the CMPCn interrupt request output.
Note 3. The operation stabilization wait time is required after enabling comparator operation (HCMPON bit = 1). As for the value, refer to
section 32, Electrical Characteristics.
Note 4. Rewriting the CINV bit or CDFS[1:0] bits may generate a CMPCn interrupt request and POE source. Before changing these bits,
set the registers in the POE so that comparator output is not used for output disabling control. After changing these bits, also set
the corresponding interrupt status flag (IR) in the interrupt request register and the POE comparator channel n output detection
flag (n = 0 to 2) to 0.
CEG[1:0] Bits (Comparator Edge Interrupt Detection Select)
These bits select which edge of comparator output signal is used to generate an interrupt request.
The valid edge is set for the signal after the comparator polarity is selected by the CINV bit and the filter is selected by
CDFS[1:0] bits.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
CEG[1:0] —
0 0 0 0
4
*
1, 2,
*
3
b1 b0
COE CINV
0 0
Description
0: Comparator output not inverted
1: Comparator output inverted
0: Comparator output disabled (the output signal is fixed to 0)
1: Comparator output enabled
This bit is read as 0. The write value should be 0.
b4 b3
0 0: Interrupt request is not generated.
0 1: Rising edge
1 0: Falling edge
1 1: Both edges
4
*
b6 b5
0 0: Noise filter not used
0 1: Sampling frequency is PCLK/8.
1 0: Sampling frequency is PCLK/16.
1 1: Sampling frequency is PCLK/32.
0: Operation stopped (the output signal is fixed to 0)
1: Operation enabled (input to the comparator pins is enabled)
28. Comparator C (CMPC)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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