Renesas RX100 Series User Manual page 737

RX13T Group
ACKBR Bit (Receive Acknowledge)
This bit is used to store the acknowledge bit information received from the receive device in transmit mode.
[Setting condition]
 When 1 is received as the acknowledge bit with the ICCR2.TRS bit set to 1
[Clearing conditions]
 When 0 is received as the acknowledge bit with the ICCR2.TRS bit set to 1
 When 1 is written to the ICCR1.IICRST bit while the ICCR1.ICE bit is 0 (RIIC reset)
ACKBT Bit (Transmit Acknowledge)
This bit is used to set the bit to be sent at the acknowledge timing in receive mode.
[Setting condition]
 When 1 is written to this bit with the ACKWP bit set to 1
[Clearing conditions]
 When 0 is written to this bit with the ACKWP bit set to 1
 When stop condition issuance is detected (when a stop condition is detected with the ICCR2.SP bit set to 1)
 When 1 is written to the ICCR1.IICRST bit while the ICCR1.ICE bit is 0 (RIIC reset)
ACKWP Bit (ACKBT Write Protect)
This bit is used to control the modification of the ACKBT bit.
RDRFS Bit (RDRF Flag Set Timing Select)
This bit is used to select the RDRF flag set timing in receive mode and also to select whether to hold the SCL0 line low
at the falling edge of the eighth SCL clock cycle.
When the RDRFS bit is 0, the SCL0 line is not held low at the falling edge of the eighth SCL clock cycle, and the RDRF
flag is set to 1 at the rising edge of the ninth SCL clock cycle.
When the RDRFS bit is 1, the RDRF flag is set to 1 at the rising edge of the eighth SCL clock cycle and the SCL0 line is
held low at the falling edge of the eighth SCL clock cycle. The low-hold of the SCL0 line is released by writing a value
to the ACKBT bit.
After data is received with this setting, the SCL0 line is automatically held low before the acknowledge bit is sent. This
enables processing to send ACK (ACKBT bit is 0) or NACK (ACKBT bit is 1) according to receive data.
WAIT Bit (WAIT)
This bit is used to control whether to hold the period between the ninth SCL clock cycle and the first SCL clock cycle
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low until the I C-bus receive data register (ICDRR) is completely read each time single-byte data is received in receive
mode.
When the WAIT bit is 0, the receive operation is continued without holding the period between the ninth and the first
SCL clock cycle low. When both the RDRFS and WAIT bits are 0, continuous receive operation is enabled with the
double buffer.
When the WAIT bit is 1, the SCL0 line is held low from the falling edge of the ninth clock cycle until the ICDRR register
value is read each time single-byte data is received. This enables receive operation in byte units.
Note: When the value of the WAIT bit is to be read, be sure to read the ICDRR register beforehand.
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SMBS Bit (SMBus/I C-bus Select)
Setting this bit to 1 selects the SMBus and enables the ICSER.HOAE bit.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
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24. I C-bus Interface (RIICa)
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