Irq Pin Digital Filter Enable Register 0 (Irqflte0) - Renesas RX100 Series User Manual

RX13T Group
14.2.8

IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0)

Address(es): ICU.IRQFLTE0 0008 7510h
b7 b6
— —
Value after reset: 0 0
Bit Symbol Bit Name
b0 FLTEN0 IRQ0 Digital Filter Enable
b1 FLTEN1 IRQ1 Digital Filter Enable
b2 FLTEN2 IRQ2 Digital Filter Enable
b3 FLTEN3 IRQ3 Digital Filter Enable
b4 FLTEN4 IRQ4 Digital Filter Enable
b5 FLTEN5 IRQ5 Digital Filter Enable
b7, b6 — Reserved
FLTENi Bit (IRQi Digital Filter Enable) (i = 0 to 5)
This bit enables the digital filter used for the IRQi pin.
The digital filter is enabled when the FLTENi bit is 1, and disabled when the FLTENi bit is 0.
The IRQi pin level is sampled at the sampling clock cycle specified with the IRQFLTC0.FCLKSELi[1:0] bits. When the
sampled level matches three times, the output level from the digital filter changes.
For details of the digital filter, see section 14.4.7, Digital Filter .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
FLTEN FLTEN FLTEN FLTEN
5 4 3 2
0 0 0 0
b1 b0
FLTEN FLTEN
1 0
0 0
Description
0: Digital filter is disabled
1: Digital filter is enabled
These bits are read as 0. The write value should be 0.
14. Interrupt Controller (ICUb)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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