A/D Sample-And-Hold Circuit Control Register (Adshcr) - Renesas RX100 Series User Manual

RX13T Group
26.2.14

A/D Sample-and-Hold Circuit Control Register (ADSHCR)

Address(es): S12AD.ADSHCR 0008 9066h
b15 b14
— —
Value after reset: 0 0
Bit Symbol
b7 to b0 SSTSH[7:0]
b10 to b8 SHANS[2:0]
b15 to b11 —
ADSHCR sets the parameters related to channel-dedicated sample-and-hold circuits.
SSTSH[7:0] Bits (Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting)
These bits set the sampling time for the channel-dedicated sample-and-hold circuits. If one state is one ADCLK (A/D
conversion clock) cycle and the ADCLK clock is 32 MHz, one state is 31.25 ns. The initial value is 26 states. If the
impedance of analog input signal source is too high to secure sufficient sampling time or if the ADCLK clock is slow, the
sampling time can be adjusted. The SSTSH[7:0] bits should be set while the ADCSR.ADST bit is 0. The sampling time
must be set to a value that is 4 states or more and is 255 or less. Also, the sampling state setting value should be at least
the specified test condition in section 32.5, A/D Conversion Characteristics .
SHANS[2:0] Bits (Channel-Dedicated Sample-and-Hold Circuit Bypass Select)
These bits select whether to use or not use (bypass) AN000 to AN002 channel-dedicated sample-and-hold circuits. The
SHANS[0] bit selects AN000, SHANS[1] bit selects AN001, and SHANS[2] bit selects AN002. The SHANS[2:0] bits
should be set while the ADCSR.ADST bit is 0.
If any channel from among AN000 to AN002 is selected for group B or C while operation is in group scan mode under
group priority control, make the setting to bypass the channel-dedicated sample-and-hold circuit.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
— — — SHANS[2:0]
0 0 0 0
Bit Name
Channel-Dedicated Sample-and-Hold
Circuit Sampling Time Setting
Channel-Dedicated Sample-and-Hold
Circuit Bypass Select
Reserved
b9 b8 b7 b6
0 0 0 0
Description
Set the sampling time (4 to 255 states).
Select whether to use or not use (bypass) AN000 to
AN002 channel-dedicated sample-and-hold circuits.
0: Bypass the channel-dedicated sample-and-hold
circuits.
1: Use the channel-dedicated sample-and-hold circuits.
These bits are read as 0. The write value should be 0.
26. 12-Bit A/D Converter (S12ADF)
b5 b4 b3 b2
SSTSH[7:0]
0 1 1 0
Page 832 of 1041
b1 b0
1 0
R/W
R/W
R/W
R/W