Renesas RX100 Series User Manual page 745

32-bit mcu
Hide thumbs Also See for RX100 Series:
Table of Contents

Advertisement

RX13T Group
For 10-bit address format: SARUy.FS bit = 1
 When the received slave address does not match a value of (11110b + SARUy.SVA[1:0] bits) with the
ICSER.SARyE bit set to 1 (slave address y detection enabled)
This flag is set to 0 at the rising edge of the ninth SCL clock cycle in the first byte.
 When the received slave address matches a value of (11110b + SARUy.SVA[1:0] bits) and the following address
does not match the SARLy value with the ICSER.SARyE bit set to 1 (slave address y detection enabled)
This flag is set to 0 at the rising edge of the ninth SCL clock cycle in the second byte.
GCA Flag (General Call Address Detection Flag)
[Setting condition]
 When the received slave address matches the general call address (0000 000b + 0 (write)) with the ICSER.GCAE
bit set to 1 (general call address detection is enabled)
This flag is set to 1 at the rising edge of the ninth SCL clock cycle in the first byte.
[Clearing conditions]
 When 0 is written to the GCA flag after reading GCA flag to be 1
 When a stop condition is detected
 When the received slave address does not match the general call address (0000 000b + 0 (write)) with the
ICSER.GCAE bit set to 1 (general call address detection is enabled)
This flag is set to 0 at the rising edge of the ninth SCL clock cycle in the first byte.
 When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
DID Flag (Device-ID Address Detection Flag)
[Setting condition]
 When the first byte received immediately after a start condition or restart condition is detected matches a value of
(device ID (1111 100b) + 0 (write)) with the ICSER.DIDE bit set to 1 (device-ID address detection is enabled)
This flag is set to 1 at the rising edge of the ninth SCL clock cycle in the first byte.
[Clearing conditions]
 When 0 is written to the DID flag after reading DID flag to be 1
 When a stop condition is detected
 When the first byte received immediately after a start condition or restart condition is detected does not match a
value of (device ID (1111 100b)) with the ICSER.DIDE bit set to 1 (device-ID address detection is enabled)
This flag is set to 0 at the rising edge of the ninth SCL clock cycle in the first byte.
 When the first byte received immediately after a start condition or restart condition is detected matches a value of
(device ID (1111 100b) + 0 (write)) and the second byte does not match any of slave addresses 0 to 2 with the
ICSER.DIDE bit set to 1 (device-ID address detection is enabled)
This flag is set to 0 at the rising edge of the ninth SCL clock cycle in the second byte.
 When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
HOA Flag (Host Address Detection Flag)
[Setting condition]
 When the received slave address matches the host address (0001 000b) with the ICSER.HOAE bit set to 1 (host
address detection is enabled)
This flag is set to 1 at the rising edge of the ninth SCL clock cycle in the first byte.
[Clearing conditions]
 When 0 is written to the HOA flag after reading HOA flag to be 1
 When a stop condition is detected
 When the received slave address does not match the host address (0001 000b) with the ICSER.HOAE bit set to 1
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
2
24. I
C-bus Interface (RIICa)
Page 745 of 1041

Advertisement

Table of Contents
loading

Table of Contents