Control Field 0 Compare Enable Register (Cf0Cr); Control Field 0 Receive Data Register (Cf0Rr); Primary Control Field 1 Data Register (Pcf1Dr) - Renesas RX100 Series User Manual

RX13T Group
23.2.30

Control Field 0 Compare Enable Register (CF0CR)

Address(es): SCI12.CF0CR 0008 B32Ah
b7 b6
CF0CE CF0CE
7 6
Value after reset: 0 0
Bit Symbol Bit Name
b0 CF0CE0 Control Field 0 Bit 0 Compare Enable
b1 CF0CE1 Control Field 0 Bit 1 Compare Enable
b2 CF0CE2 Control Field 0 Bit 2 Compare Enable
b3 CF0CE3 Control Field 0 Bit 3 Compare Enable
b4 CF0CE4 Control Field 0 Bit 4 Compare Enable
b5 CF0CE5 Control Field 0 Bit 5 Compare Enable
b6 CF0CE6 Control Field 0 Bit 6 Compare Enable
b7 CF0CE7 Control Field 0 Bit 7 Compare Enable
23.2.31

Control Field 0 Receive Data Register (CF0RR)

Address(es): SCI12.CF0RR 0008 B32Bh
b7 b6
0 0
Value after reset:
CF0RR is a readable register that holds the value received in Control Field 0.
23.2.32

Primary Control Field 1 Data Register (PCF1DR)

Address(es): SCI12.PCF1DR 0008 B32Ch
b7 b6
Value after reset: 0 0
PCF1DR is an 8-bit readable and writable register that holds the 8-bit primary value for comparison with Control Field 1.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
CF0CE CF0CE CF0CE CF0CE
5 4 3 2
0 0 0 0
b5 b4 b3 b2
0 0 0 0
b5 b4 b3 b2
0 0 0 0
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
CF0CE CF0CE
1 0
0 0
Description
0: Comparison with bit 0 of Control Field 0 is disabled.
1: Comparison with bit 0 of Control Field 0 is enabled.
0: Comparison with bit 1 of Control Field 0 is disabled.
1: Comparison with bit 1 of Control Field 0 is enabled.
0: Comparison with bit 2 of Control Field 0 is disabled.
1: Comparison with bit 2 of Control Field 0 is enabled.
0: Comparison with bit 3 of Control Field 0 is disabled.
1: Comparison with bit 3 of Control Field 0 is enabled.
0: Comparison with bit 4 of Control Field 0 is disabled.
1: Comparison with bit 4 of Control Field 0 is enabled.
0: Comparison with bit 5 of Control Field 0 is disabled.
1: Comparison with bit 5 of Control Field 0 is enabled.
0: Comparison with bit 6 of Control Field 0 is disabled.
1: Comparison with bit 6 of Control Field 0 is enabled.
0: Comparison with bit 7 of Control Field 0 is disabled.
1: Comparison with bit 7 of Control Field 0 is enabled.
b1 b0
0 0
b1 b0
0 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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