Renesas RX100 Series User Manual page 739

RX13T Group
NACKE Bit (NACK Reception Transfer Abort Enable)
This bit is used to specify whether to continue or discontinue the transfer operation when NACK is received from the
slave device in transmit mode. Normally, set this bit to 1.
When NACK is received with the NACKE bit set to 1, the next transfer operation is aborted.
When the NACKE bit is 0, the next transfer operation is continued regardless of the received acknowledge content.
For details on the NACK reception transfer abort function, refer to section 24.8.2, NACK Reception Transfer Abort
Function .
SCLE Bit (SCL Synchronous Circuit Enable)
This bit is used to specify whether to synchronize the SCL clock with the SCL input clock. Normally, set this bit to 1.
When the SCLE bit is set to 0 (no SCL synchronous circuit used), the RIIC does not synchronize the SCL clock with the
SCL input clock. In this setting, the RIIC outputs the SCL clock with the transfer rate set in registers ICBRH and ICBRL
regardless of the SCL0 line state. For this reason, if the bus load of the I
value or if the SCL clock output overlaps in multiple masters, the short-cycle SCL clock that does not meet the
specification may be output. When no SCL synchronous circuit is used, it also affects the issuance of a start condition,
restart condition, and stop condition, and the continuous output of extra SCL clock cycles.
This bit must not be set to 0 except for checking the output of the set transfer rate.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
2
24. I C-bus Interface (RIICa)
2
C-bus line is much larger than the specification
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