Renesas RX100 Series User Manual page 529

RX13T Group
Table 20.2 shows I/O pins to be used by the POE.
Table 20.2 POE I/O Pins
Pin Name I/O
POE0# Input
POE8# Input
POE10# Input
Table 20.3 shows output-level comparisons with pin combinations.
Table 20.3 Pin Combinations
Pin Combination
MTIOC3B and MTIOC3D
MTIOC4A and MTIOC4C
MTIOC4B and MTIOC4D
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Description
Request signal to put the outputs of the MTU complementary PWM output pins (MTU3, MTU4 pins) in
the high-impedance state, and is also capable of controlling the other target pins by register settings.
Request signal to put the output of the MTU0 pins in the high-impedance state, and is also capable of
controlling the other target pins by register settings.
Is capable of controlling every target pins by register settings.
I/O Description
Output The MTU complementary PWM output pins (MTU3 and MTU4 pins) are in the high-
impedance state when two pins of the set simultaneously output the active level (low level
when the MTU.TOCR1A.OLSP bit is 0 or high level when the OLSP bit is 1 while the
OLSEN bit in the ALR1 register is 0 and the MTU.TOCR1A.TOCS bit is 0, low level when
Output
the OLS1P, OLS1N, OLS2P, OLS2N, OLS3P, and OLS3N bits in the MTU.TOCR2A register
are 0 or high level when these bits are 1 while the OLSEN bit in the ALR1 register is 0 and
the MTU.TOCR1A.TOCS bit is 1, or low level when the OLSG0A, OLSG0B, OLSG1A,
OLSG1B, OLSG2A, and OLSG2B bits in the ALR1 register are 0 and high level when these
Output
bits are 1 while the OLSEN bit in the ALR1 register is 1) for at least one cycle of the
peripheral module clock (PCLK).
Pin combinations for output comparison can be selected by registers of POE.
20. Port Output Enable 3 (POE3C)
Page 529 of 1041