States Of Pins In Master And Slave Modes; Ss Function In Master Mode; Ss Function In Slave Mode - Renesas RX100 Series User Manual

RX13T Group
23.8.1

States of Pins in Master and Slave Modes

The direction (input or output) of pins for the simple SPI mode interface differs according to whether the device is a
master (SCR.CKE[1:0] = 00b or 01b and SPMR.MSS = 0) or slave (SCR.CKE[1:0] = 10b or 11b and SPMR.MSS = 1).
Table 23.29 lists the states of pins according to the mode and the level on the SSn# pin.
Table 23.29 States of Pins by Mode and Input Level on the SSn# Pin
Mode Input on SSn# Pin
1
Master mode* High level
(transfer can proceed)
Low level
(transfer cannot proceed)
Slave mode High level
(transfer cannot proceed)
Low level
(transfer can proceed)
Note 1. When there is only a single master (SPMR.SSE = 0), transfer is possible regardless of the input level on the SSn# pin (this is
equivalent to input of a high level on the SSn# pin). Since the SSn# pin function is not required, the pin is available for other
purposes.
Note 2. The SMOSIn pin output is in the high-impedance state when serial transmission is disabled (SCR.TE bit = 0).
Note 3. The SCKn pin output is in the high-impedance state when serial transmission is disabled (SCR.TE and RE bits = 00b) in a multi-
master configuration (SPMR.SSE = 1).
23.8.2

SS Function in Master Mode

Setting the CKE[1:0] bits in the SCR to 00b and the MSS bit in the SPMR to 0 selects master operation. The SSn# pin is
not used in single-master configurations (SPMR.SSE = 0), so transmission or reception can proceed regardless of the
value of the SSn# pin.
When the level on the SSn# pin is high in a multi-master configuration (SPMR.SSE = 1), a master device outputs clock
signals from the SCKn pin before starting transmission or reception to indicate that there are no other masters or another
master is performing reception or transmission. When the level on the SSn# pin is low in a multi-master configuration
(SPMR.SSE = 1), there are other masters, and this indicates that transmission or reception is in progress. At this time the
SMOSIn output and SCKn pins will be placed in the high-impedance state and starting transmission or reception will not
be possible. Furthermore, the value of the SPMR.MFF bit will be 1, indicating a mode fault error. In a multi-master
configuration, start error processing by reading SPMR.MFF flag. Also, even if a mode fault error occurs while
transmission or reception is in progress, transmission or reception will not be stopped, but the SMOSIn and SCKn pin
output will be placed in the high-impedance state after the completion of the transfer.
Control a general port pin to produce the SS output signal from the master.
23.8.3

SS Function in Slave Mode

Setting the CKE[1:0] bits in the SCR to 10b and the MSS bit in the SPMR to 1 selects slave operation. When the level on
the SSn# pin is high, the SMISOn output pin will be in the high-impedance state and clock input through the SCKn pin
will be ignored. When the level on the SSn# pin is low, clock input through the SCKn pin will be effective and
transmission or reception can proceed.
If the input on the SSn# pin changes from low to high level during transmission or reception, the SMISOn output pin will
be placed in the high-impedance state. Meanwhile, the internal processing for transmission or reception will continue at
the rate of the clock input through the SCKn pin until processing for the character currently being transmitted or received
is completed, after which it stops. At that time, an interrupt (the appropriate one from among TXI, RXI, and TEI) will be
generated.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
23. Serial Communications Interface (SCIg, SCIh)
State of SMOSIn Pin State of SMISOn Pin
Output for data Input for received data
2
transmission*
High-impedance Input for received data
(but disabled)
Input for received data High-impedance
(but disabled)
Input for received data Output for data
transmission
State of SCKn Pin
3
Clock output*
High-impedance
Clock input
(but disabled)
Clock input
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