Chain Transfer When The Counter Is 0 - Renesas RX100 Series User Manual

RX13T Group
16.6.2

Chain Transfer When the Counter is 0

The second data transfer is performed only when the transfer counter is set to 0 in the first data transfer, and the first data
transfer information is repeatedly changed in the second data transfer. Repeating this chain transfer enables transfers to
be repeated more than 256 times.
The following shows an example of configuring a 128-Kbyte input buffer to addresses 20 0000h to 21 FFFFh (where the
input buffer is set so that its lower address starts with 0000h). Figure 16.25 shows a chain transfer when the counter is 0.
(1) Set normal transfer mode for input data for the first data transfer. Set the following:
Transfer source address: Fixed, the CRA register is 0000h (65,536 times), the MRB.CHNE bit is 1 (chain transfer is
enabled), the MRB.CHNS bit is 1 (chain transfer is performed only when the transfer counter becomes 0), and the
MRB.DISEL bit is 0 (an interrupt request to the CPU is generated on completion of the specified number of data
transfers).
(2) Prepare the upper 8 bits (in this case, 21h and 20h) of the start address at every 65,536 times of the transfer
destination address for the first data transfer in another area (such as ROM).
(3) For the second data transfer, set repeat transfer mode (source is repeat area) for rewriting the transfer destination
address of the first data transfer. The transfer destination is the address where the upper 8 bits of the DAR register in
the first transfer information is allocated. In this case, set the MRB.CHNE bit to 0 (chain transfer is disabled) and
the MRB.DISEL bit to 0 (an interrupt request to the CPU is generated on completion of the specified number of data
transfers). In this case, set the transfer counter to 2.
(4) When a transfer request is accepted, the first data transfer is executed. When transfer is executed 65,536 times and
the transfer counter of the first data transfer becomes 0, the second data transfer is started and the upper 8 bits of the
transfer destination address of the first data transfer is set to 21h. At this time, the lower 16 bits of the transfer
destination address and the transfer counter of the first data transfer have become 0000h.
(5) In succession, when another transfer request is accepted, the first data transfer is executed. When transfer is
executed 65,536 times and the transfer counter of the first data transfer becomes 0, the second data transfer is started
and the upper 8 bits of the transfer destination address of the first data transfer is set to 20h. At this time, the lower
16 bits of the transfer destination address and the transfer counter of the first data transfer have become 0000h.
(6) Steps (4) and (5) above are repeated infinitely. Because the second data transfer is in repeat transfer mode, no
interrupt request to the CPU is generated.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
16. Data Transfer Controller (DTCb)
Page 287 of 1041