Renesas RX100 Series User Manual page 596

RX13T Group
CKE[1:0] Bits (Clock Enable)
These bits select the clock source and SCKn pin function.
The combination of the settings of these bits and of the SEMR.ACS0 bit sets the internal MTU clock.
TEIE Bit (Transmit End Interrupt Enable)
Enables or disables a TEI interrupt request.
A TEI interrupt request is disabled by setting the TEIE bit to 0.
2
In simple I C mode, the TEI is allocated to the interrupt on completion of issuing a start, restart, or stop condition (STI).
In this case, the TEIE bit can be used to enable or disable the STI.
MPIE Bit (Multi-Processor Interrupt Enable)
When this bit is set to 1 and the data with the multi-processor bit set to 0 is received, the data is not read and setting the
status flags ORER and FER in the SSR register to 1 is disabled. When the data with the multi-processor bit set to 1 is
received, the MPIE bit is automatically cleared to 0, and normal reception is resumed. For details, refer to section 23.4,
Multi-Processor Communications Function .
When the data with the multi-processor bit set to 0 is received, the receive data is not transferred from the RSR to the
RDR, a receive error is not detected, and setting the flags ORER and FER to 1 is disabled.
When the data with the multi-processor bit set to 1 is received, the MPB bit is set to 1, the MPIE bit is automatically
cleared to 0, the RXI and ERI interrupt requests are enabled (if the SCR.RIE bit is set to 1), and setting the flags ORER
and FER to 1 is enabled.
Set the MPIE bit to 0 if multi-processor communications function is not to be used.
RE Bit (Receive Enable)
Enables or disables serial reception.
When this bit is set to 1, serial reception is started by detecting the start bit in asynchronous mode or the synchronous
clock input in clock synchronous mode. Note that the SMR register should be set prior to setting the RE bit to 1 in order
to designate the reception format.
Even if reception is halted by setting the RE bit to 0, the ORER, FER, PER, and RDRF flags in the SSR register are not
affected and the previous value is retained.
TE Bit (Transmit Enable)
Enables or disables serial transmission.
When this bit is set to 1, serial transmission is started by writing transmit data to TDR. Note that SMR should be set prior
to setting the TE bit to 1 in order to designate the transmission format.
RIE Bit (Receive Interrupt Enable)
Enables or disables RXI and ERI interrupt requests.
An RXI interrupt request is disabled by setting the RIE bit to 0.
An ERI interrupt request can be canceled by reading 1 from the ORER, FER, or PER flag in the SSR register and then
setting the flag to 0, or setting the RIE bit to 0.
TIE Bit (Transmit Interrupt Enable)
Enables or disables TXI interrupt request.
A TXI interrupt request is disabled by setting the TIE bit to 0.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
23. Serial Communications Interface (SCIg, SCIh)
Page 596 of 1041