Data Transfer Controller (Dtcb); Overview - Renesas RX100 Series User Manual

RX13T Group
16.

Data Transfer Controller (DTCb)

This MCU incorporates a data transfer controller (DTC).
The DTC is triggered by an interrupt request to perform data transfers.
In addition to the conventional methods of DTC transfer (normal, repeat, block, and chain), DTCb supports sequential
transfer, in which it handles a series of transfers made up of a combination of the other methods. In sequential transfer,
the data that is initially transferred selects one from possible 256 sequences for execution. The DTCb can divide one
sequence into several transfers depending on how the parts of the sequence are combined.
16.1

Overview

Table 16.1 lists the specifications of the DTC, and Figure 16.1 shows a block diagram of the DTC.
Table 16.1 DTC Specifications
Item
Number of transfer channels
Transfer modes
Chain transfer
Sequence transfer
Transfer space
Data transfer units
CPU interrupt source
Read skip
Write-back skip
Write-back disable
Displacement addition
Low power consumption function
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Description
 The same number as all interrupt sources that can start the DTC transfer.
 Normal transfer mode
A single transfer request leads to a single data transfer.
 Repeat transfer mode
A single transfer request leads to a single data transfer.
The transfer address is returned to the transfer start address after the number of data
transfers corresponding to "repeat size".
The maximum number of repeat transfers is 256, and the maximum data transfer size is 256 ×
32 bits, 1024 bytes.
 Block transfer mode
A single transfer request leads to the transfer of a single block.
The maximum block size is 256 × 32 bits = 1024 bytes.
 Multiple types of data transfers can sequentially be executed in response to a single request.
 Either "performed only when the transfer counter becomes 0" or "every time" can be selected.
A series of complicated transfers can be registered as a sequence. Any sequence can be
selected by the transfer data and executed.
 Only one trigger source can be set at a time.
 Up to 256 sequences for a single trigger source
 The data that is initially transferred in response to a transfer request determines a sequence
 The whole sequence can be executed on a single request, or be suspended in the middle of
the sequence and resumed on the next transfer request (division of sequence).
 In short-address mode: 16 Mbytes
(Areas from 0000 0000h to 007F FFFFh and FF80 0000h to FFFF FFFFh except reserved
areas)
 In full-address mode: 4 Gbytes
(Area from 0000 0000h to FFFF FFFFh except reserved areas)
 Single data: 1 byte (8 bits), 1 word (16 bits), 1 longword (32 bits)
 Single block size: 1 to 256 data
 An interrupt request can be generated to the CPU on a request source for a data transfer.
 An interrupt request can be generated to the CPU after a single data transfer.
 An interrupt request can be generated to the CPU after data transfer of specified volume.
Reading of the transfer information can be skipped when the same transfer is repeated.
Write-back of the transferred data that is not updated can be skipped when the address of the
transfer source or destination is fixed.
Allows disabling the write-back of transfer information.
The displacement value can be added to the transfer source address (for each transfer
information)
Module stop state can be set.
16. Data Transfer Controller (DTCb)
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