Instructions Converted Into Multiple Micro-Operations And Pipeline Processing - Renesas RX100 Series User Manual

RX13T Group
2.8.2.2

Instructions Converted into Multiple Micro-Operations and Pipeline Processing

The table below lists the instructions that are converted into multiple micro-operations. The number of cycles in the table
indicates the number of cycles during no-wait memory access.
Table 2.14 Instructions that are Converted into Multiple Micro-Operations (1/2)
Instruction
Arithmetic/logic instructions
(memory source operand)
Arithmetic/logic instructions
(division)
Arithmetic/logic instruction
(multiplier: 32 × 32 → 64 bits)
(register-register, register-
immediate)
Arithmetic/logic instruction
(multiplier: 32 × 32 → 64 bits)
(memory source operand)
Arithmetic/logic instructions
(multiply-and-accumulate
operation)
Arithmetic/logic instruction (64-bit
signed saturation processing for
the RMPA instruction)
Data transfer instructions
(memory-memory transfer)
Bit manipulation instructions
(memory source operand)
Transfer instruction
(load operation)
Transfer instruction (save
operation of multiple registers)
Transfer instruction (restore
operation of multiple registers)
Transfer instruction
(register-register)
Transfer instruction
(memory-register)
Branch instructions
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Mnemonic (indicates the common operation when
the size is omitted)
 {ADC, ADD, AND, MAX, MIN, MUL, OR, SBB, SUB,
XOR} "[Rs], Rd"/"dsp[Rs], Rd"
 {CMP, TST} "[Rs], Rs2"/"dsp[Rs], Rs2"
 DIV "[Rs], Rd / dsp[Rs], Rd"
 DIVU"[Rs], Rd / dsp[Rs], Rd"
 {EMUL, EMULU} "#IMM, Rd"/"Rs, Rd"
 {EMUL, EMULU} "[Rs], Rd"/"dsp[Rs], Rd"
 RMPA.B
 RMPA.W
 RMPA.L
 SATR
 MOV "[Rs], [Rd]"/"dsp[Rs], [Rd]"/"[Rs], dsp[Rd]"/
"dsp[Rs], dsp[Rd]"
 PUSH "[Rs]"/"dsp[Rs]"
 {BCLR, BNOT, BSET} "#IMM, [Rd]"/"#IMM, dsp[Rd]"/
"Rs, [Rd]"/"Rs, dsp[Rd]"
 BM Cnd "#IMM, [Rd]"/"#IMM, dsp[Rd]"
 BTST "#IMM, [Rs]"/"#IMM, dsp[Rs]"/"Rs, [Rs2]"/"Rs,
dsp[Rs2]
 POPC "CR"
 PUSHM "Rs-Rs2"
 POPM "Rs-Rs2"
 XCHG "Rs, Rd"
 XCHG "[Rs], Rd"/"dsp[Rs], Rd"
 RTS
 RTSD "#IMM"
 RTSD "#IMM, Rd-Rd2"
Reference
Figure Number of Cycles
Figure 2.10 3
— 5 to 22
— 4 to 20
Figure 2.12 2
— 4
— 6+7×floor(n/4)+4×(n%4)
n: Number of processing
1
bytes*
— 6+5×floor(n/2)+4×(n%2)
n: Number of processing
1
words*
— 6+4n
n: Number of processing
1
longwords*
— 3
Figure 2.11 3
Figure 2.11 3
— Throughput: 3
2
Latency: 4*
— n
n: Number of registers*
— Throughput: n
Latency: n+1
n: Number of
2, 4
registers* *
Figure 2.13 2
Figure 2.14 2
— 5
— 5
— Throughput: n<5?5:1+n
Latency: n<4?5:2+n
n: Number of registers*
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