Numbers Of Cycles For Response To Interrupts - Renesas RX100 Series User Manual

RX13T Group
2.8.4

Numbers of Cycles for Response to Interrupts

Table 2.15 lists numbers of cycles taken by processing for response to interrupts.
Table 2.15 Numbers of Cycles for Response to Interrupts
Type of Interrupt Request/Details of Processing
ICU
Judgment of priority order
CPU
Number of cycles from notification to acceptance of
the interrupt request
CPU Pre-processing by hardware
Saving the current PC and PSW values in RAM
(or in control registers in the case of the fast interrupt)
Reading of the vector
Branching to the start of the exception handling
routine
Times calculated from the values in Table 2.15 will be applicable when access to memory from the CPU is processed
with no waiting. The ROM and RAM in products of this MCU allow such access. Numbers of cycles for response to
interrupts can be minimized by placing program code (and vectors) in ROM and the stack in RAM. Furthermore, place
the addresses where the exception handling routine start on 8-byte boundaries.
For information on the number of cycles from notification to acceptance of the interrupt request, indicated by N in the
table above, see Table 2.13, Instructions that are Converted into a Single Micro-Operation , and Table 2.14,
Instructions that are Converted into Multiple Micro-Operations .
The timing of interrupt acceptance depends on the state of the pipelines. For more information on this, refer to section
13.3.1, Acceptance Timing and Saved PC Value .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Fast Interrupt
2 cycles
N cycles
(varies with the instruction being executed at the time the interrupt was
received)
4 cycles
Other Interrupts
6 cycles
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2. CPU