Renesas RX100 Series User Manual page 605

RX13T Group
BCP2 Bit (Base Clock Pulse 2)
Selects the number of base clock cycles in a 1-bit data transfer time in smart card interface mode. Set this bit in
combination with the SMR.BCP[1:0] bits.
Table 23.9 Combinations of the SCMR.BCP2 Bit and SMR.BCP[1:0] Bits
SCMR.BCP2 Bit SMR.BCP[1:0] Bits
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Note 1. S is the value of S in BRR (refer to section 23.2.11, Bit Rate Register (BRR)).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
23. Serial Communications Interface (SCIg, SCIh)
Number of Base Clock Cycles for 1-Bit Transfer Period
0 93 clock cycles (S = 93)*
1 128 clock cycles (S = 128)*
0 186 clock cycles (S = 186)*
1 512 clock cycles (S = 512)*
0 32 clock cycles (S = 32)*
1 64 clock cycles (S = 64)*
0 372 clock cycles (S = 372)*
1 256 clock cycles (S = 256)*
1
1
1
1
1
(Initial Value)
1
1
1
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