Renesas RX100 Series User Manual page 34

RX13T Group
Table 1.1 Outline of Specifications (3/3)
Classification Module/Function
Communication Serial communications
functions interfaces (SCIg, SCIh)
2
I C bus interface (RIICa)
12-bit A/D converter (S12ADF)
Comparator C (CMPC)
D/A converter (DA) for generating comparator C
reference voltage
CRC calculator (CRC)
Data operation circuit (DOC)
Power supply voltages/Operating frequencies
Supply current
Operating temperature range
Packages
Debugging interface
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Description
 3 channels (channel 1 and 5: SCIg, channel 12: SCIh)
 SCIg
Serial communications modes: Asynchronous, clock synchronous, and smart-card interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from MTU timers
Start-bit detection: Level or edge detection is selectable.
2
Simple I C
Simple SPI
9-bit transfer mode
Bit rate modulation
 SCIh (The following functions are added to SCIg)
Supports the serial communications protocol, which contains the start frame and information frame
Supports the LIN format
 1 channel
 Communications formats: I
2 C bus format/SMBus format
 Master mode or slave mode selectable
 Supports fast mode
 12 bits (8 channels × 1 unit)
 12-bit resolution
 Minimum conversion time: 1.4 µs per channel when the ADCLK is operating at 32 MHz
 Operating modes
Scan mode (single scan mode, continuous scan mode, and 3 group scan mode)
Group A priority control (only for 3 group scan mode)
 Sampling variable
Sampling time can be set up for each channel
 Self-diagnostic function
 Double trigger mode (A/D conversion data duplicated)
 Assist on analog input disconnection detection
 A/D conversion start conditions
A software trigger, a trigger from a timer (MTU), or an external trigger signal
 Sample-and-hold function
Sample-and-hold circuit included (3 channels)
 Amplification of input signals by a programmable gain amplifier (3 channels)
Amplification rate: 2.000 times, 2.500 times, 3.077 times, 5.000 times, 8.000 times, 10.000 times
(total of 6 steps)
 3 channels
 Function to compare the reference voltage and the analog input voltage
 Reference voltage: Select from among two voltages
 Analog input voltage: Select from among four voltages
 1 channel
 8-bit resolution
 Output voltage: 0 to AVCC0
 Reference voltage generation circuit for comparator C
 CRC code generation for arbitrary amounts of data in 8-bit units
 Select any of three generating polynomials:
8 2 16 15 2
X + X + X + 1, X + X + X
 Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.
Comparison, addition, and subtraction of 16-bit data
VCC = 2.7 to 5.5V: 32 MHz
11 mA at 32 MHz (typ.)
–
D version: 40 to +85°C, G version:
48-pin LFQFP (PLQP0048KB-B) 7 × 7mm, 0.5mm pitch
32-pin LQFP (PLQP0032GB-A) 7 × 7mm, 0.8mm pitch
FINE interface
16 12 5
+ 1, or X + X + X + 1
–
40 to +105°C
1. Overview
Page 34 of 1041