Determining Priority; Multiple Interrupts; Fast Interrupt - Renesas RX100 Series User Manual

RX13T Group
14.4.4

Determining Priority

Interrupt priority is determined for each interrupt request destination.
The priority for each interrupt request destination is determined as follows.
(1) Determining Priority when the CPU is the Request Destination of the Interrupt
A source selected for the fast interrupt has the highest priority. After that, an interrupt source with a larger value of the
interrupt priority level select bits (IPR[3:0]) in IPRn takes priority. If interrupts with the same priority level are generated
by multiple sources, the source with the smallest vector number takes precedence.
(2) Determining Priority when the DTC is the Request Destination of the Interrupt
The IPR[3:0] bits in IPRn (n = interrupt vector number) have no effect. An interrupt source with a smaller vector number
takes precedence.
14.4.5

Multiple Interrupts

To enable multiple interrupts of the CPU, set the PSW.I bit to 1 (interrupt enabled) in the handling routine of accepted
interrupts.
The PSW.IPL[3:0] bits immediately after processing branches to the interrupt handling routine are set to the same value
as the interrupt priority level of the accepted interrupt request. If an interrupt request which has an interrupt level higher
than that of the PSW.IPL[3:0] bits is generated at this time, this interrupt request (for multiple interrupts) is accepted.
If the interrupt priority level of the accepted interrupt request is 15 (fast interrupt or interrupt when IPR[3:0] are set to
1111b), multiple interrupts are not generated.
14.4.6

Fast Interrupt

The fast interrupt is an interrupt for executing a faster interrupt response by the CPU, so only one of the interrupt sources
can be assigned.
The interrupt priority level of the fast interrupt is 15 (highest) regardless of the setting of the IPR[3:0] bits in IPRn (n =
interrupt vector number). In addition, the fast interrupt is accepted with precedence over other interrupt sources with
level 15. However, when the value of the PSW.IPL[3:0] bits are 1111b (priority level 15), even the fast interrupt cannot
be accepted.
To assign an interrupt source to the fast interrupt, specify the vector number of the source in the FIR.FVCT[7:0] bits, and
set the FIR.FIEN bit to 1 (fast interrupt is enabled).
For details on the fast interrupt, see section 2, CPU and section 13, Exception Handling .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
14. Interrupt Controller (ICUb)
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