Renesas RX100 Series User Manual page 426

RX13T Group
(1) Example of Complementary PWM Mode Setting Procedure
Figure 19.45 shows an example of the complementary PWM mode setting procedure.
Complementary PWM mode
Stop count operation
Count clock, counter clear
source selection
Brushless DC motor control
setting
TCNT setting
Inter-channel synchronization
setting
TGR setting
Enable/disable dead time
generation
Dead time, carrier period
setting
Enable PWM cyclic output,
set PWM output level
Complementary PWM mode
setting
Enable waveform output
Set MPC.
Start count operation
<Complementary PWM mode>
Figure 19.45 Example of Complementary PWM Mode Setting Procedure
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
[1] Set the TSTRA.CST3 and TSTRA.CST4 bits to 0 to stop the TCNT count operation.
Specify complementary PWM mode while MTU3.TCNT and MTU4.TCNT are stopped.
[2] Set the TCR.TPSC[2:0] and TCR.CKEG[1:0] bits of MTU3 and MTU4 to select the same
count clock source and clock edge for MTU3 and MTU4.
Set the TCR.CCLR[2:0] bits only when restarting by synchronous clearing with another
channel during complementary PWM operation.
[1]
[3] To control a brushless DC motor, set the TGCRA.BDC bit and set the feedback signal
input source and output chopping or gate signal direct output (only when MTU3 and
MTU4 are used).
[2]
[4] Set the dead time in MTU3.TCNT. Set MTU4.TCNT to 0000h.
[3]
[5] Make this setting only when restarting by synchronous clearing with another channel
during complementary PWM mode operation. In this case, set the TSYRA register to
synchronize the channel generating the synchronous clear with MTU3 and MTU4.
[4]
[6] When MTU3 is used, set the PWM output duty ratio in the duty registers (MTU3.TGRB,
MTU4.TGRA, and MTU4.TGRB) and buffer registers (MTU3.TGRD, MTU4.TGRC, and
MTU4.TGRD).
Be sure to set the same value in each pair of the duty registers (MTU3.TGRD,
[5]
MTU4.TGRC, and MTU4.TGRD) and buffer registers (MTU3.TGRB, MTU4.TGRA, and
MTU4.TGRB).
Only when the double buffer function is used, set the buffer registers (MTU3.TGRE,
[6]
MTU4.TGRE, and MTU4.TGRF).
[7] This setting is necessary only when no dead time should be generated. Make
appropriate settings in the TDERA register so that no dead time generated.
[7]
[8] Set the dead time in the TDDRA register, 1/2 the PWM period in the TCDRA register and
TCBRA register, and 1/2 the PWM period plus the dead time in MTU3.TGRA and
MTU3.TGRC.
[8]
When no dead time generation is selected, set 1 in the TDDRA register and
1/2 the PWM period + 1 in MTU3.TGRA and MTU3.TGRC.
[9] [9] Set the PSYE bit in the TOCR1A register to enable or disable toggle output synchronized
with the PWM period, and set the OLSP and OLSN bits to select the PWM output level.
When specifying the PWM output level using the TOCR2A and TOLBRA in buffer
operation, refer to Timer Output Level Buffer Registers (TOLBRA).
[10]
[10] Select complementary PWM mode in MTU3.TMDR1. Specify the buffer operation (BFA
= 1) of MTU3.TGRA and the buffer operation (BFB = 1) of MTU3.TGRB.
Only when the double buffer function is used, set the TMDR2A register to enable the
[11]
double buffer function.
[11] Set the TOERA register to enable or disable output from the PWM output pin. Then, set
the MTU3.TIORH, MTU3.TIORL, MTU4.TIORH, and MTU4.TIORL to 00h.
[12]
[12] Set the MPU and the port mode register (PMR) of the I/O ports.
[13] Set the TSTRA.CST3 and TSTRA.CST4 bits to 1 simultaneously to start count
[13]
operation.
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Page 426 of 1041