Secondary Control Field 1 Data Register (Scf1Dr); Control Field 1 Compare Enable Register (Cf1Cr); Control Field 1 Receive Data Register (Cf1Rr) - Renesas RX100 Series User Manual

RX13T Group
23.2.33

Secondary Control Field 1 Data Register (SCF1DR)

Address(es): SCI12.SCF1DR 0008 B32Dh
b7 b6
Value after reset: 0 0
PCF1DR is an 8-bit readable and writable register that holds the 8-bit secondary value for comparison with Control Field
1.
23.2.34

Control Field 1 Compare Enable Register (CF1CR)

Address(es): SCI12.CF1CR 0008 B32Eh
b7 b6
CF1CE CF1CE
7 6
Value after reset: 0 0
Bit Symbol Bit Name
b0 CF1CE0 Control Field 1 Bit 0 Compare Enable
b1 CF1CE1 Control Field 1 Bit 1 Compare Enable
b2 CF1CE2 Control Field 1 Bit 2 Compare Enable
b3 CF1CE3 Control Field 1 Bit 3 Compare Enable
b4 CF1CE4 Control Field 1 Bit 4 Compare Enable
b5 CF1CE5 Control Field 1 Bit 5 Compare Enable
b6 CF1CE6 Control Field 1 Bit 6 Compare Enable
b7 CF1CE7 Control Field 1 Bit 7 Compare Enable
23.2.35

Control Field 1 Receive Data Register (CF1RR)

Address(es): SCI12.CF1RR 0008 B32Fh
b7 b6
0 0
Value after reset:
CF1RR is a readable register that holds the value received in Control Field 1.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
0 0 0 0
b5 b4 b3 b2
CF1CE CF1CE CF1CE CF1CE
5 4 3 2
0 0 0 0
b5 b4 b3 b2
0 0 0 0
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
0 0
b1 b0
CF1CE CF1CE
1 0
0 0
Description
0: Comparison with bit 0 of Control Field 1 is disabled.
1: Comparison with bit 0 of Control Field 1 is enabled.
0: Comparison with bit 1 of Control Field 1 is disabled.
1: Comparison with bit 1 of Control Field 1 is enabled.
0: Comparison with bit 2 of Control Field 1 is disabled.
1: Comparison with bit 2 of Control Field 1 is enabled.
0: Comparison with bit 3 of Control Field 1 is disabled.
1: Comparison with bit 3 of Control Field 1 is enabled.
0: Comparison with bit 4 of Control Field 1 is disabled.
1: Comparison with bit 4 of Control Field 1 is enabled.
0: Comparison with bit 5 of Control Field 1 is disabled.
1: Comparison with bit 5 of Control Field 1 is enabled.
0: Comparison with bit 6 of Control Field 1 is disabled.
1: Comparison with bit 6 of Control Field 1 is enabled.
0: Comparison with bit 7 of Control Field 1 is disabled.
1: Comparison with bit 7 of Control Field 1 is enabled.
b1 b0
0 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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