Buffer Operation And Compare Match In Reset-Synchronized Pwm Mode - Renesas RX100 Series User Manual

RX13T Group
19.6.15

Buffer Operation and Compare Match in Reset-Synchronized PWM Mode

When setting buffer operation in reset-synchronized PWM mode, set the BFA and BFB bits in MTU4.TMDR1 to 0. The
MTIOC4C pin cannot output waveforms if the BFA bit in MTU4.TMDR1 is set to 1. Likewise, the MTIOC4D pin
cannot output waveforms if the BFB bit in MTU4.TMDR1 is set to 1.
In reset-synchronized PWM mode, buffer operation in MTU3 and MTU4 depends on the settings in the BFA and BFB
bits of MTU3.TMDR1. For example, if the BFA bit in MTU3.TMDR1 is set to 1, MTU3.TGRC functions as a buffer
register for MTU3.TGRA. At the same time, MTU4.TGRC functions as a buffer register for MTU4.TGRA.
While the MTU3.TGRC and MTU3.TGRD are operating as buffer registers, a TGImn interrupt (m = C, D; n = 3, 4) is
not generated.
Figure 19.134 shows an example of MTU3.TGR, MTU4.TGR, MTIOC3, and MTIOC4 operation with the BFA and
BFB bits in MTU3.TMDR1 set to 1 and the BFA and BFB bits in MTU4.TMDR1 set to 0.
MTU3.TGRA
MTU3.TGRC
MTU3.TGRB, MTU4.TGRA
MTU4.TGRB
MTU3.TGRD, MTU4.TGRC
MTU4.TGRD
0000h
MTIOC3A
MTIOC3B
MTIOC3D
MTIOC4A
MTIOC4C
MTIOC4B
MTIOC4D
TGIC interrupt request signal
TGID interrupt request signal
Figure 19.134 Buffer Operation and Compare Match in Reset-Synchronized PWM Mode
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
MTU3.TCNT
Point a
Point b
Not set
Not set
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Buffer data transferred by compare match A3
MTU3.TGRA
MTU3.TGRC
MTU3.TGRB, MTU3.TGRD
MTU4.TGRA, MTU4.TGRC
MTU4.TGRB, MTU4.TGRD
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