Renesas RX100 Series User Manual page 765

32-bit mcu
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RX13T Group
Automatic low hold
(to prevent wrong transmission)
S
1
SCL0
SDA0
b7
BBSY
MST
TRS
Transmit data (7-bit address + R)
TDRE
TEND
RDRF
ICDRT
ICDRS
XXXX (Initial value/last data for reception)
ICDRR
ACKBT
X (ACK/NACK)
ACKBR
START
ST
Write 1
Write data to ICDRT register
to ST bit
(7-bit address + R)
[2]
[3]
Figure 24.12
Master Receive Operation Timing (1) (7-Bit Address Format, When RDRFS bit is 0)
Automatic low hold (to prevent wrong transmission)
S
1 to 7
SCL0
SDA0
b7
Upper 10 bits
BBSY
MST
TRS
Transmit data (upper 10 bits + W)
TDRE
TEND
RDRF
Upper 10 bits + W
ICDRT
ICDRS
Upper 10 bits + W
ICDRR
ACKBT
X (ACK/NACK)
ACKBR
START
ST
RS
Write data to ICDRT
Write 1
register
to ST bit
(11110b + 2 bits + W)
[2]
Figure 24.13
Master Receive Operation Timing (2) (10-Bit Address Format, When RDRFS bit is 0)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Master transmit mode
2
3
4
5
6
7
b6
b5
b4
b3
b2
b1
7-bit slave address
Receive data (7-bit address + R)
7-bit address + R
8
9
1 to 8
9
ACK
ACK
b1
b0
b7
b0
W
Lower 10 bits
Transmit data (lower 10 bits)
Lower 10 bits
Lower 10 bits
0 (ACK)
Write data to
Clear
Write 1
ICDRT register
START flag
to RS bit
(lower 8 bits)
[3]
Master receive mode
8
9
1
2
3
4
b0
ACK
b7
b6
b5
b4
R
DATA 1
7-bit address + R
XXXX (Initial value/last data for reception)
0 (ACK)
0 (ACK)
Read ICDRR register
(Dummy read)
[4]
Sr
1
2
3
4
b7
b6
b5
b4
Upper 10-bit addresses (11110b + 2 bits)
Transmit data (upper 10 bits + R)
Upper 10 bits + R
XXXX (Initial value/last data for reception)
0 (ACK)
0 (ACK)
Write data to ICDRT
register
(11110b + 2 bits + R)
2
24. I
C-bus Interface (RIICa)
5
6
7
8
9
1
ACK
b3
b2
b1
b0
b7
Receive data (DATA 1)
DATA 1
Read ICDRR register
(DATA 1)
[5]
Master transmit mode
Master receive mode
5
6
7
8
9
1
ACK
b3
b2
b1
b0
b7
R
Transmit data (upper 10 bits + R)
Upper 10 bits + R
XXXX (Initial value/last data for reception)
0 (ACK)
Read ICDRR register
(Dummy read)
[4]
Page 765 of 1041
2
3
4
b6
b5
b4
DATA 2
DATA 2
DATA 1
0 (ACK)
2
3
4
b6
b5
b4
DATA 1
DATA 1

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