Block Diagram - Renesas RX100 Series User Manual

RX13T Group
1.3

Block Diagram

Figure 1.2 shows a block diagram.
ROM
RAM
RX CPU
FPU
Clock
generation
circuit
ICUb: Interrupt controller
DTCb: Data transfer controller
IWDTa: Independent watchdog timer
CRC: CRC (cyclic redundancy check) calculator
SCIg, SCIh: Serial communications interface
2
RIICa: I C bus interface
Figure 1.2 Block Diagram
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
ICUb
MTU3c × 6 channels
DTCb
CMT × 2 channels (unit 0)
12-bit A/D converter × 8 channels
Programmable gain amplifier
Sample and hold circuit
8-bit D/A converter × 1 channel
Comparator C × 3 channels
MTU3c: Multi-function timer pulse unit 3
POE3C: Port output enable 3
DOC: Data operation circuit
CAC: Clock frequency accuracy measurement circuit
FPU: Floating process unit
E2 DataFlash
IWDTa
CRC
SCIg × 2 channels
SCIh × 1 channel
RIICa × 1 channel
POE3C
× 3 channels
× 3 channels
DOC
CAC
1. Overview
Port 1
Port 2
Port 3
Port 4
Port 7
Port 9
Port A
Port B
Port D
Port E
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