Vector Table; Interrupt Vector Table - Renesas RX100 Series User Manual

Hide thumbs Also See for RX100 Series:

Table of Contents

Vector Table

There are two types of interrupts detected by the interrupt controller: maskable interrupts and non-maskable interrupts.

When the CPU accepts an interrupt or non-maskable interrupt, it acquires a 4-byte vector address from the vector table.

The interrupt vector table is placed in the 1024-byte range (4 bytes × 256 sources) beginning at the address specified in

the interrupt table register (INTB) of the CPU. Write a value to the INTB register before enabling interrupts. The value

written to the INTB register should be a multiple of 4.

Executing an INT instruction or BRK instruction leads to the generation of an unconditional trap. The same range of

memory as shown in Table 14.3, Interrupt Vector Table , is used for the vectors for unconditional traps. The vector for

BRK instructions is vector 0 while the vector numbers for INT instructions are specifiable as numbers in the range from

Table 14.3 lists details of the interrupt vectors. Details of the headings in Table 14.3 are listed below.

Source of interrupt request

Vector address offset

Form of interrupt detection

CPU interrupt

Start the DTC

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

Name of the source for generation of the interrupt request

Name of the interrupt

Vector number for the interrupt

Value of the offset from the base address for the vector table

"Edge" or "level" as the method for detection of the interrupt

"  " in this column indicates usability as a CPU interrupt.

"  " in this column indicates usability as a request for DTC transfer.

"  " in this column indicates usability as a request for return from software-standby mode.

Name of the IER register and bit corresponding to the vector number

Name of the IPR register corresponding to the interrupt source

Name of the DTCER register corresponding to the DTC trigger

14. Interrupt Controller (ICUb)

Page 215 of 1041