Initialization Of The Port Direction Register (Pdr) - Renesas RX100 Series User Manual

RX13T Group
17.4

Initialization of the Port Direction Register (PDR)

Initialize reserved bits in the PDR register according to Table 17.3 and Table 17.4 .
 The blank columns in Table 17.3 and Table 17.4 indicate the bits corresponding to the pins listed in Table 17.1,
Specifications of I/O Ports .
The corresponding bits should be set to 1 (output) or 0 (input) depending on the user system.
 The columns other than the blank columns in Table 17.3 and Table 17.4 indicate reserved bits.
A reserved bit should be set to 0 (input) or 1 (output) according to Table 17.3 and Table 17.4 .
When setting a value to a reserved bit, access in byte units.
Table 17.3 PDR Register Settings in 48-Pin Packages
PDR Register
Port Symbol b7
PORT1 0
PORT2 0
PORT3
PORT4
PORT7 0
PORT9 0
PORTA 0
PORTB
PORTD 0
Table 17.4 PDR Register Settings in 32-Pin Packages
PDR Register
Port Symbol b7
PORT1 0
PORT2 0
PORT3
PORT4 1
PORT7 0
PORT9 0
PORTA 0
PORTB
PORTD 0
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b6 b5 b4
0 0 0
0 0
0 0
0 0
0 0 0
b6 b5 b4
0 0 0
0 0 1
0 0
1 1
0 0
0 0 0
1 1
1 1 1
b3 b2 b1
0 0
0
0 0 0
0 0
0
0 0
b3 b2 b1
0 0
1 1 0
0 0 0
0 0
0 0 0
1 0 0
17. I/O Ports
b0
0
0
0
0
0
b0
1
0
0
1
0
0
0
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