Clock Output Control - Renesas RX100 Series User Manual

RX13T Group
23.6.8

Clock Output Control

Clock output can be fixed to high or low using the SCR.CKE[1:0] bits when the SMR.GM bit is 1. When the CKE[1:0]
bits are set to 01b (clock output), the base clock is output from the SCK pin. For the settings of the base clock frequency
(bit rate), refer to section 23.2.11, Bit Rate Register (BRR) . When the CKE[1:0] bits are set to 00b (output fixed low)
or 10b (output fixed to high), the SCK pin can be fixed to low or high.
Figure 23.44 shows a timing chart when the clock output is controlled.
If changing the CKE[1:0] bits while the SMR.GM bit is 0 (non-GSM mode), a pulse of unexpected width may output
from SCK pin because the result is immediately reflected to the SCK pin.
Base clock
When the SCR.GM bit is 1
SCR.CKE[1:0] bits
SCK
When the SCR.GM bit is 0
SCR.CKE[1:0] bits
SCK
Figure 23.44 Clock Output Control
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
01b 00b
01b
23. Serial Communications Interface (SCIg, SCIh)
01b 10b
00b
Hi-Z
01b
01b
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