Correspondence Between Option Function Select Register 0 (Ofs0) And Iwdt Registers; Usage Notes; Refresh Operations; Clock Divide Ratio Setting - Renesas RX100 Series User Manual

RX13T Group
22.3.8 Correspondence between Option Function Select Register 0 (OFS0) and IWDT
Registers
Table 22.5 lists the correspondence between option function select register 0 (OFS0) used in auto-start mode and the
registers used in register start mode.
Do not change the OFS0 register setting during IWDT operation.
For details on the OFS0 register, refer to section 7.2.1, Option Function Select Register 0 (OFS0) .
Table 22.5

Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers

Target of Control Function
Counter Timeout period selection
Clock frequency divide ratio selection OFS0.IWDTCKS[3:0]
Window start position selection
Window end position selection
Reset output or Reset output or interrupt request
interrupt request output selection
output
Count stop Sleep mode count stop control
22.4

Usage Notes

22.4.1

Refresh Operations

When making the settings to control the timing of refreshing, consider variations in the range of errors due to the
accuracy of the PCLK and IWDTCLK and set values which ensure that refreshing is possible.
22.4.2

Clock Divide Ratio Setting

Satisfy the frequency of the peripheral module clock (PCLK) ≥ 4 × (the frequency of the count source after divide).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
22. Independent Watchdog Timer (IWDTa)
OFS0 Register
(Enabled in Auto-Start Mode)
OFS0.IWDTSTRT = 0
OFS0.IWDTTOPS[1:0]
OFS0.IWDTRPSS[1:0]
OFS0.IWDTRPES[1:0]
OFS0.IWDTRSTIRQS
OFS0.IWDTSLCSTP
IWDT Registers
(Enabled in Register Start Mode)
OFS0.IWDTSTRT = 1
IWDTCR.TOPS[1:0]
IWDTCR.CKS[3:0]
IWDTCR.RPSS[1:0]
IWDTCR.RPES[1:0]
IWDTRCR.RSTIRQS
IWDTCSTPR.SLCSTP
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