Renesas RX100 Series User Manual page 233

RX13T Group
ICLK
synchronization
CPU
Instruction bus
Operand bus
Memory
bus 1
Internal main bus 1
Internal main bus 2
Peripheral
Figure 15.1 Bus Configuration
Table 15.2 Addresses Assigned for Each Bus
Address
0000 0000h to 0000 FFFFh
0008 0000h to 0008 7FFFh
0008 8000h to 0009 FFFFh
000A 0000h to 000B FFFFh
0010 0000h to 00FF FFFFh
8000 0000h to FEFF FFFFh
FF00 0000h to FFFF FFFFh
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Memory
bus 2
RAM ROM
Internal
peripheral bus 1
DTC (s)
module
Note: The solid arrows indicate the directions of the access being requested of the bus master.
Note: DTC (m) is used for bus mastership, while DTC (s) is for register access.
Bus
Memory bus 1
Internal peripheral bus 1
Internal peripheral bus 2
Internal peripheral bus 3
Internal peripheral bus 6
Memory bus 2
Internal peripheral
buses 2 and 3
Peripheral Peripheral
• • •
module module
Operation synchronized with
PCLKB and PCLKD
Area
Bus error
monitoring section
DTC (m)
Internal
peripheral bus 6
ROM
E2
DataFlash
(P/E)
Operation synchronized
with FCLK
RAM
Peripheral I/O registers
E2 DataFlash memory and ROM
(for programming/erasure)
ROM
(for reading only)
Page 233 of 1041
15. Buses