A/D Sampling State Register N (Adsstrn) (N = 0 To 7, O) - Renesas RX100 Series User Manual

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A/D Sampling State Register n (ADSSTRn) (n = 0 to 7, O)

Address(es): S12AD.ADSSTR0 0008 90E0h, S12AD.ADSSTR1 0008 90E1h, S12AD.ADSSTR2 0008 90E2h,

S12AD.ADSSTR3 0008 90E3h, S12AD.ADSSTR4 0008 90E4h, S12AD.ADSSTR5 0008 90E5h,

S12AD.ADSSTR6 0008 90E6h, S12AD.ADSSTR7 0008 90E7h,

S12AD.ADSSTRO 0008 90DFh

Value after reset:

The ADSSTRn register sets the sampling time for analog input.

If one state is one ADCLK (A/D conversion clock) cycle and the ADCLK clock is 32 MHz, one state is 31.25 ns. The

initial value is 13 states. If the impedance of analog input signal source is too high to secure sufficient sampling time or if

the ADCLK clock is slow, the sampling time can be adjusted. The ADSSTRn register should be set while the

ADCSR.ADST bit is 0. The lower-limit value for sampling time differs depending on the PCLK to ADCLK frequency

Set a value that is 5 states or more when PCLK to ADCLK frequency ratio = 1:1, 2:1, 4:1, or 8:1.

Table 26.9 shows the relationship between the A/D sampling state register and the relevant channels.

For details, refer to section 26.3.5, Analog Input Sampling Time and Scan Conversion Time .

Relationship between A/D Sampling State Register and Relevant Channels

Note 1. When performing A/D conversion of the internal reference voltage, the sampling time should be 5 μs or longer.

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

ADSSTR0 register

ADSSTR1 register

ADSSTR2 register

ADSSTR3 register

ADSSTR4 register

ADSSTR5 register

ADSSTR6 register

ADSSTR7 register

ADSSTRO register

Relevant Channels

AN000, Self-Diagnosis

Internal reference voltage*

26. 12-Bit A/D Converter (S12ADF)

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