Renesas HD6473937RXV Manuals

Manuals and User Guides for Renesas HD6473937RXV. We have 1 Renesas HD6473937RXV manual available for free PDF download: Manual

Renesas HD6473937RXV Manual (523 pages)

Brand: Renesas | Category: Microcontrollers | Size: 2.06 MB

Table of Contents
7
Overview
15
Internal Block Diagram
19
Pin Arrangement and Functions
20
Pin Arrangement
20
Pin Functions
21
Cpu
27
Overview
27
Features
27
Address Space
28
Register Configuration
28
Register Descriptions
29
General Registers
29
Control Registers
29
Initial Register Values
30
Data Formats
31
Data Formats in General Registers
32
Memory Data Formats
33
Addressing Modes
34
Effective Address Calculation
36
Instruction Set
40
Data Transfer Instructions
42
Arithmetic Operations
44
Logic Operations
45
Shift Operations
45
Bit Manipulations
47
Branching Instructions
51
System Control Instructions
53
Block Data Transfer Instruction
54
Basic Operational Timing
56
Access to On-Chip Memory (RAM, ROM)
56
Access to On-Chip Peripheral Modules
57
CPU States
59
Overview
59
Program Execution State
60
Program Halt State
60
Exception-Handling State
60
Memory Map
61
Application Notes
64
Notes on Data Access
64
Notes on Bit Manipulation
66
Notes on Use of the EEPMOV Instruction
72
Exception Handling
73
Overview
73
Reset
73
Reset Sequence
73
Interrupt Immediately after Reset
74
Interrupts
75
Overview
75
Interrupt Control Registers
77
External Interrupts
86
Internal Interrupts
87
3.3.5 Interrupt Operations
88
Interrupt Response Time
93
Application Notes
94
Notes on Stack Area Use
94
Notes on Rewriting Port Mode Registers
95
Notes on Interrupt Request Flag Clearing Methods
97
Clock Pulse Generators
99
Overview
99
Block Diagram
99
System Clock and Subclock
99
System Clock Generator
100
Subclock Generator
103
Prescalers
105
Note on Oscillators
106
Definition of Oscillation Settling Standby Time
106
Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator Element)
108
Power-Down Modes
109
Overview
109
System Control Registers
112
Sleep Mode
117
Transition to Sleep Mode
117
Clearing Sleep Mode
117
Clock Frequency in Sleep (Medium-Speed) Mode
118
Standby Mode
119
Transition to Standby Mode
119
Clearing Standby Mode
119
Oscillator Settling Time after Standby Mode Is Cleared
119
Standby Mode Transition and Pin States
120
Notes on External Input Signal Changes Before/After Standby Mode
121
Watch Mode
123
Transition to Watch Mode
123
Clearing Watch Mode
123
Oscillator Settling Time after Watch Mode Is Cleared
123
Notes on External Input Signal Changes Before/After Watch Mode
123
Subsleep Mode
124
Transition to Subsleep Mode
124
Clearing Subsleep Mode
124
Subactive Mode
125
Transition to Subactive Mode
125
Clearing Subactive Mode
125
Operating Frequency in Subactive Mode
125
Active (Medium-Speed) Mode
126
Transition to Active (Medium-Speed) Mode
126
Clearing Active (Medium-Speed) Mode
126
Operating Frequency in Active (Medium-Speed) Mode
126
Direct Transfer
127
Overview of Direct Transfer
127
Direct Transition Times
128
Notes on External Input Signal Changes Before/After Direct Transition
130
Module Standby Mode
131
Setting Module Standby Mode
131
Clearing Module Standby Mode
131
Rom
133
Overview
133
Block Diagram
133
PROM Mode
134
Setting to PROM Mode
134
Socket Adapter Pin Arrangement and Memory Map
134
Programming
137
Writing and Verifying
137
Programming Precautions
142
Reliability of Programmed Data
143
Ram
145
Overview
145
7.1.1 Block Diagram
145
I/O Ports
147
Overview
147
Port 1
149
Overview
149
Register Configuration and Description
149
Pin Functions
154
Pin States
156
MOS Input Pull-Up
156
Port 2 [Chip Internal I/O Port]
157
Overview
157
Register Configuration and Description
157
Function
161
States
161
Port 3
162
Overview
162
Register Configuration and Description
162
Pin Functions
165
Pin States
167
MOS Input Pull-Up
167
Port 4
168
Overview
168
Register Configuration and Description
168
Pin Functions
170
Pin States
171
Port 5
172
Overview
172
Register Configuration and Description
172
Pin Functions
174
Pin States
175
MOS Input Pull-Up
175
Port 6
176
Overview
176
Register Configuration and Description
176
Pin Functions
178
Pin States
178
MOS Input Pull-Up
178
Port 7
179
Overview
179
Register Configuration and Description
179
Pin Functions
181
Pin States
181
Port 8
182
Overview
182
Register Configuration and Description
182
Pin Functions
183
Port 9
184
Overview
184
Register Configuration and Description
184
Pin Functions
186
Pin States
186
Port a
187
Overview
187
Register Configuration and Description
187
Pin States
188
Port B
189
Overview
189
Register Configuration and Description
189
Input/Output Data Inversion Function
190
Overview
190
Register Configuration and Descriptions
190
Note on Modification of Serial Port Control Register
192
Application Note
192
The Management of the Un-Use Terminal
192
Timers
193
Overview
193
Timer a
194
Overview
194
Register Descriptions
196
Timer Operation
200
Timer a Operation States
201
Application Note
201
Timer C
202
Overview
202
Register Descriptions
204
Timer Operation
207
Timer C Operation States
209
Timer F
210
Overview
210
Register Descriptions
213
CPU Interface
220
Operation
223
Application Notes
226
Timer G
229
Overview
229
Register Descriptions
231
Noise Canceler
235
Operation
237
Application Notes
241
Timer G Application Example
246
Watchdog Timer
247
Overview
247
Register Descriptions
248
Timer Operation
252
Watchdog Timer Operation States
253
Section 10 Serial Communication Interface
255
Overview
255
SCI1 [Chip Internal Function]
256
Overview
256
Register Descriptions
258
Operation
264
Interrupt Source
266
Application Note
267
Sci3
268
Overview
268
Register Descriptions
272
Operation
294
Interrupts
322
Application Notes
323
Section 11 A/D Converter
329
Overview
329
Features
329
Block Diagram
330
Pin Configuration
331
Register Configuration
331
Register Descriptions
332
A/D Result Registers (ADRRH, ADRRL)
332
A/D Mode Register (AMR)
332
A/D Start Register (ADSR)
334
Clock Stop Register 1 (CKSTPR1)
335
Operation
336
A/D Conversion Operation
336
Start of A/D Conversion by External Trigger Input
336
A/D Converter Operation Modes
337
Interrupts
337
Typical Use
337
Application Notes
341
Section 12 FLEX Roaming Decoder
343
Overview
343
Features
343
System Block Diagram
344
12.1.3 Functional Block Diagram
346
SPI Packets
347
Packet Communication Initiated by the Host
347
Packet Communication Initiated by the FLEX Decoder
348
Host-To-Decoder Packet Map
350
Decoder-To-Host Packet Map
352
Host-To-Decoder Packet Descriptions
352
Checksum Packet
352
Configuration Packet
355
Control Packet
358
All Frame Mode Packet
359
Operator Messaging Address Enable Packet
361
Roaming Control Packet
361
Timing Control Packet
364
Receiver Line Control Packet
365
Receiver Control Configuration Packets
365
12.3.10 Frame Assignment Packets
369
12.3.11 User Address Enable Packet
370
User Address Assignment Packets
371
Decoder-To-Host Packet Descriptions
372
Block Information Word Packet
373
Address Packet
374
Vector Packet
375
Message Packet
380
Roaming Status Packet
380
Receiver Shutdown Packet
383
Status Packet
384
Part ID Packet
386
Application Notes
388
Receiver Control
388
Message Building
391
Building a Fragmented Message
393
Operation of a Temporary Address
396
Using the Receiver Shutdown Packet
398
Timing Diagrams (Reference Data)
401
SPI Timing
401
Start-Up Timing
403
Reset Timing
404
Section 13 Electrical Characteristics
405
Absolute Maximum Ratings
405
Electrical Characteristics
406
Power Supply Voltage and Operating Range
406
DC Characteristics
408
AC Characteristics
412
A/D Converter Characteristics
415
Operation Timing
416
Output Load Circuit
419
Resonator Equivalent Circuit
419
Usage Note
420
Appendix A CPU Instruction Set
421
Instructions
421
Operation Code Map
429
Number of Execution States
431
Appendix B Internal I/O Registers
437
Addresses
437
Functions
440
Appendix C I/O Port Block Diagrams
492
Block Diagrams of Port 1
492
Block Diagrams of Port 2 [Chip Internal I/O Port]
496
Block Diagrams of Port 3
500
Block Diagrams of Port 4
507
Block Diagram of Port 5
511
Block Diagram of Port 6
512
Block Diagram of Port 7
513
Block Diagrams of Port 8
514
Block Diagram of Port 9
515
Block Diagram of Port a
516
Block Diagram of Port B
517
Appendix D Port States in the Different Processing States
518
Appendix E List of Product Codes
519
Appendix F Package Dimensions
520

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