A/D Conversion Restarting Timing And Termination Timing; Notes On Scan End Interrupt Handling; Module Stop Function Setting; Notes On Entering Low Power Consumption States - Renesas RX100 Series User Manual

RX13T Group
26.6.3

A/D Conversion Restarting Timing and Termination Timing

It takes a maximum of six ADCLK cycles for the idle analog unit of the 12-bit A/D converter to be restarted by setting
the ADCSR.ADST bit to 1. It takes a maximum of three ADCLK cycles for the operating analog unit of the 12-bit A/D
converter to be terminated by setting the ADCSR.ADST bit to 0.
26.6.4

Notes on Scan End Interrupt Handling

When scanning the same analog input twice using any trigger, the first A/D-converted data is overwritten with the second
A/D-converted data in the case that the CPU does not complete reading the A/D-converted data by the time the A/D
conversion of the first analog input for the second scan ends after the first scan end interrupt is generated.
26.6.5

Module Stop Function Setting

Operation of the 12-bit A/D converter can be disabled or enabled by setting module stop control register. The initial
setting is for operation of the 12-bit A/D converter to be halted. Register access is enabled by releasing the module stop
state.
After the module stop state is released, wait for 1 μs to start A/D conversion. For details, refer to section 11, Low
Power Consumption .
26.6.6

Notes on Entering Low Power Consumption States

Before entering the module stop state or software standby mode, make sure to stop A/D conversion. Here, set the
ADCSR.ADST bit to 0, and secure certain period of time until the analog unit of the 12-bit A/D converter is stopped.
Follow the procedure given below to secure this time.
Set the ADCSR.ADST bit to 0 by following the procedure in Figure 26.33 Procedure for Clear Operation by Software
through the ADCSR.ADST Bit. Then wait for three clock cycles of ADCLK before entering the module stop mode or
software standby mode.
26.6.7

Notes on Canceling Software Standby Mode

After software standby mode is canceled, wait until the crystal oscillation stabilization time or the PLL circuit
stabilization time elapses, and then wait for 1 μs before starting A/D conversion. For details, refer to section 11, Low
Power Consumption .
26.6.8

Error in Absolute Accuracy When Disconnection Detection Assistance is in Use

Using disconnection detection assistance leads to an error in absolute accuracy of the A/D converter. This is because an
error voltage is input to the analog input pins due to the resistive voltage division between the pull-up or pull-down
resistor (Rp) and the resistance of the signal source (Rs). The disconnection detection assist function should be used
while ADPGACR.PnENAMP = 0 (does not use the amplifier in the PGA) and ADSHCR.SHANS = 0 (bypass the
sample-and-hold circuits). This error in absolute accuracy is calculated from the following formula. Only use
disconnection detection assistance after thorough evaluation.
Maximum error in absolute accuracy (LSB) = 4095 × Rs / Rp
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
26. 12-Bit A/D Converter (S12ADF)
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