Status Flags; Reset Output; Interrupt Sources - Renesas RX100 Series User Manual

RX13T Group
22.3.4

Status Flags

The IWDTSR.REFEF and IWDTSR.UNDFF flags retain the source of the reset signal output from the IWDT or the
source of the interrupt request from the IWDT.
Thus, after release from the reset state or interrupt request generation, read the IWDTSR.REFEF and IWDTSR.UNDFF
flags to check for the reset or interrupt source.
For each flag, writing 0 clears the bit and writing 1 has no effect.
Leaving the status flags unchanged does not affect operation. If the flags are not cleared, at the time of the next reset or
interrupt request from the IWDT, the earlier reset or interrupt source is cleared and the new reset or interrupt source is
written.
After 0 is written to each flag, up to three IWDTCLK cycles and two PCLK cycles are required before the value is
reflected.
22.3.5

Reset Output

When the IWDTRCR.RSTIRQS bit is set to 1 in register start mode or when the IWDTRSTIRQS bit in option function
select register 0 (OFS0) is set to 1 in auto-start mode, a reset signal is output when an underflow in the counter or a
refresh error occurs.
In register start mode, the counter is initialized (0000h) and kept in that state after assertion of the reset signal. After the
reset is released and the program is restarted, the counter is set up again and counting down is started by refreshing.
In auto-start mode, counting down automatically starts after the reset output.
22.3.6

Interrupt Sources

When the IWDTRCR.RSTIRQS bit is set to 0 in register start mode or when the OFS0.IWDTRSTIRQS bit is set to 0 in
auto-start mode, an interrupt (WUNI) signal is output when an underflow in the counter or a refresh error occurs. This
interrupt can be used as a non-maskable interrupt. For details, refer to section 14, Interrupt Controller (ICUb) .
Table 22.4 IWDT Interrupt Source
Name Interrupt Source
WUNI Counter underflow
Refresh error
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
22. Independent Watchdog Timer (IWDTa)
DTC Activation
Not possible
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