Dtc Setting Procedure - Renesas RX100 Series User Manual

RX13T Group
16.5

DTC Setting Procedure

Before using the DTC, set the DTC vector base register (DTCVBR). When using sequence transfer, also set the DTC
index table base register (DTCIBR).
Figure 16.24 shows the procedure to set the DTC.
Start
Set the DTCCR.RRS bit to 0
Set transfer information
(MRA, MRB, MRC, SAR, DAR, CRA, and
CRB)
Set the start address of the transfer
information in the DTC vector table.
Set the start address of the transfer
information for the sequence transfer in the
DTC index table
Set the DTCCR.RRS bit to 1
Set the ICU.DTCERn.DTCE bit to 1.
Set the ICU.IERm.IENj bit to 1.
Set the interrupt enable bit for
a request source
Set the DTCST.DTCST bit to 1
End
Figure 16.24 Procedure to Set the DTC
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Set the ICU.IERm.IENj bit corresponding to the request source
[1] Setting the DTCCR.RRS bit to 0 resets the transfer information
[1]
[2] Allocate transfer information (MRA, MRB, MRC, SAR, DAR,
[2]
[3] Set the start address of the transfer information in the DTC
[3]
[4] Setting the DTCCR.RRS bit to 1 enables skipping of the second
[4]
[5] Set the ICU.DTCERn.DTCE bit (n = interrupt vector number)
[5]
[6] Set the interrupt enable bit of the peripheral module, which is
[6]
Setting for each request
source
Common setting for DTC [7] Set the DTCST.DTCST bit to 1 (DTC module start)*
Note 1. The DTCST.DTCST bit can be set even if the setting for
[7]
16. Data Transfer Controller (DTCb)
interrupt to 0 and provide the following settings.
read skip flag. After that, transfer information read is not skipped
during the data transfer. When transfer information is updated,
be sure to make this setting.
CRA, and CRB) in the data area. For setting transfer
information, refer to section 16.2, Register Descriptions. For
how to allocate transfer information, refer to section 16.3.1,
Allocating Transfer Information and DTC Vector Table.
vector table. For how to set the DTC vector table, refer to
section 16.3.1, Allocating Transfer Information and DTC Vector
Table. When using sequence transfer, set the
DTCADMOD.SHORT bit to 0, set registers DTCIBR, DTCSQE,
and DTCDISP, and allocate the DTC index table.
and the subsequent transfer information read cycles for
continuous data transfer due to the same interrupt source. The
RRS bit can be set to 1 at any time, but this setting during data
transfer becomes valid from the next transfer. Leave the value
of the RRS bit as 0 if the value of the MRA.WBDIS bit or the
MRC.DISPE bit in any transfer information is 1 or when
sequence transfer is to be used.
that corresponds to the DTC request source to 1. Set the
ICU.IERm.IENj bit to 1. For the correspondence between
interrupt sources and DTCERn register, refer to section 14.3.1,
Interrupt Vector Table in section 14, Interrupt Controller (ICUb).
request source, to 1. When a source interrupt is generated, the
DTC starts operation. For the setting of the interrupt enable bit,
refer to the setting of the peripheral module that is to be an
request source.
each request source is not completed.
1
.
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