Renesas RX100 Series User Manual page 402

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(4) Cascaded Operation Example (c)

Figure 19.23 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE

and I1AE bits have been set to 1 to include the MTIOC2A and MTIOC1A pins in the MTU1.TGRA and MTU2.TGRA

input capture conditions, respectively. In this example, the IOA[3:0] bits in both MTU1.TIOR and MTU2.TIOR have

selected both the rising and falling edges for the input capture timing. Under these conditions, the ORed result of

MTIOC1A and MTIOC2A input is used for the MTU1.TGRA and MTU2.TGRA input capture conditions.

MTU2.TCNT value

Figure 19.23

Cascaded Operation Example (c)

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

Note 1. When either of the input signals is driven high, the selected edge of

the other cannot act as the input capture condition.

19. Multi-Function Timer Pulse Unit 3 (MTU3c)

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