Renesas RX100 Series User Manual page 763

RX13T Group
Master reception starts
Initial settings
No
ICCR2.BBSY = 0?
Yes
ICCR2.ST = 1
No
ICSR2.TDRE = 1?
Yes
Write the ICDRT register
No
ICSR2.RDRF = 1?
Yes
ICSR2.NACKF = 0?
Yes
ICMR3.WAIT = 1
Next data = last byte?
No
Dummy read the ICDRR register
No
ICSR2.RDRF = 1?
Yes
Set ICMR3.ACKBT bit
Read the ICDRR register
No
ICSR2.RDRF = 1?
Yes
ICSR2.STOP = 0
ICCR2.SP = 1
Read the ICDRR register
ICMR3.WAIT = 0
No
ICSR2.STOP = 1?
Yes
ICSR2.NACKF = 0
ICSR2.STOP = 0
Master reception ends
Figure 24.10 Example of Master Reception (7-Bit Address Format, 1 or 2 bytes)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
No
Yes
ICSR2.STOP = 0
ICCR2.SP = 1
Dummy read the ICDRR register
2
24. I C-bus Interface (RIICa)
(1) Initial settings
2
(2) Check I C-bus occupation and issue a start condition.
(3) Transmit the slave address followed by
R and check ACK.
(4) Set to WAIT
(5) Set to NACK
(When receiving 2 bytes, perform dummy
read.)
(6) Read received data
(When receiving 1 byte, perform
dummy read.)
(7) Read the last data,
release SCL by the ACKBT bit setting,
and issue a stop condition.
(8) Confirm that the stop condition
has been issued.
(9) Processing for the next transfer operation
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